commit | 718d185f1e041411a3a42862bf83c79b6e51fb36 | [log] [tgz] |
---|---|---|
author | Duncan Laurie <dlaurie@google.com> | Mon Dec 10 11:29:36 2018 -0800 |
committer | Duncan Laurie <dlaurie@chromium.org> | Fri Feb 01 21:56:07 2019 +0000 |
tree | 31080e7983d63b3a01da1c672043af52bcbbeae1 | |
parent | c01a505282526a7038463e937cbec83f704a6a89 [diff] |
vendorcode/google/chromeos: Use ACPI GPIO pin when possible Have the generated Chrome OS ACPI GPIO table provide the ACPI GPIO pin number instead of the raw GPIO number when possible. This is necessary if the OS uses a different numbering for GPIOs that are reported in ACPI than the actual underlying GPIO number. For example, if the SOC OS driver declares more pins in an ACPI GPIO bank than there are actual pins in the hardware it will have gaps in the number space. This is a reworked version of 6217e9beff16d805ca833e79a2931bcdb3d02a44 which does not try to convert CROS_GPIO_VIRTUAL. BUG=b:120686247 TEST=pass firmware_WriteProtect test on Sarien Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I3ad5099b7f2f871c7e516988f60a54eb2a75bef7 Reviewed-on: https://review.coreboot.org/c/31080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.