tree baaeb4f0353831bead527ff08cfd83e58814bd14
parent d3318cfe498bf53d8ce7d1cd55afad4a93705216
author Angel Pons <th3fanbus@gmail.com> 1600986200 +0200
committer Michael Niewöhner <foss@mniewoehner.de> 1603548234 +0000

sb/intel/lynxpoint/pcie: Fix clock gating routine

The use of `1 < 5` as a bit mask was obviously a typo. Correct it as
`1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states.

Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45713
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>