soc/intel/skylake: Use intel common support to write-protect SPI flash
BUG=chrome-os-partner:58896
Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17116
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 5a1d878..a5fb0e8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -44,6 +44,7 @@
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
+ select SOC_INTEL_COMMON_SPI_PROTECT
select SMM_TSEG
select SMP
select SSE2