tree 44ce80026673ef3abc599bee080f2e22ef1fca92
parent 25ef410423df812f626b77b695f151b6f221fa2e
author Yu-Ping Wu <yupingso@chromium.org> 1610504958 +0800
committer Hung-Te Lin <hungte@chromium.org> 1616564630 +0000

soc/mediatek: Use MRC cache API for asurada

Use the MRC cache API for asurada, and sync dramc_param.h with dram
blob (CL:*3674585). With this change, the checksum, originally stored in
flash, is replaced with a hash in TPM. In addition, in recovery boot,
full calibration will always ne performed, and the cached calibration
data will be cleared from flash.

This change increases ROMSTAGE size from 236K to 264K. Most of the
increase is caused by TPM-related functions.

Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be
moved to soc folder.

With this CL, there is no significant change in boot time. Normal AP
reboot time (fast calibration) is consistently 0.98s as before, so
this change should not affect the result of platform_BootPerf.

BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots with both full and fast calibration
BRANCH=none

Cq-Depend: chrome-internal:3674585, chrome-internal:3704751
Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>