| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * Service procedure to access various CPU registers. |
| * |
| * |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: GNB |
| * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $ |
| * |
| */ |
| /* |
| ***************************************************************************** |
| * |
| * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * * Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * * Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| * its contributors may be used to endorse or promote products derived |
| * from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| * |
| * *************************************************************************** |
| * |
| */ |
| |
| /*---------------------------------------------------------------------------------------- |
| * M O D U L E S U S E D |
| *---------------------------------------------------------------------------------------- |
| */ |
| #include "Porting.h" |
| #include "AMD.h" |
| #include "GnbLibPciAcc.h" |
| #include "GnbLibCpuAcc.h" |
| #include "Filecode.h" |
| #define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE |
| /*---------------------------------------------------------------------------------------- |
| * D E F I N I T I O N S A N D M A C R O S |
| *---------------------------------------------------------------------------------------- |
| */ |
| |
| |
| /*---------------------------------------------------------------------------------------- |
| * T Y P E D E F S A N D S T R U C T U R E S |
| *---------------------------------------------------------------------------------------- |
| */ |
| |
| |
| /*---------------------------------------------------------------------------------------- |
| * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| *---------------------------------------------------------------------------------------- |
| */ |
| |
| |
| /*----------------------------------------------------------------------------------------*/ |
| /** |
| * Read CPU (DCT) indirect registers |
| * |
| * |
| * |
| * @param[in] Address PCI address of DCT register |
| * @param[in] IndirectAddress Offset of DCT register |
| * @param[out] Value Pointer to value |
| * @param[in] Config Pointer to standard header |
| */ |
| VOID |
| GnbLibCpuPciIndirectRead ( |
| IN UINT32 Address, |
| IN UINT32 IndirectAddress, |
| OUT UINT32 *Value, |
| IN VOID *Config |
| ) |
| { |
| UINT32 OffsetRegisterValue; |
| GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); |
| do { |
| GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); |
| } while ((OffsetRegisterValue & BIT31) == 0); |
| GnbLibPciRead (Address + 4, AccessWidth32, Value, Config); |
| } |
| |
| |
| /*----------------------------------------------------------------------------------------*/ |
| /** |
| * Write CPU (DCT) indirect registers |
| * |
| * |
| * |
| * @param[in] Address PCI address of DCT register |
| * @param[in] IndirectAddress Offset of DCT register |
| * @param[in] Value Pointer to value |
| * @param[in] Config Pointer to standard header |
| */ |
| VOID |
| GnbLibCpuPciIndirectWrite ( |
| IN UINT32 Address, |
| IN UINT32 IndirectAddress, |
| IN UINT32 *Value, |
| IN VOID *Config |
| ) |
| { |
| UINT32 OffsetRegisterValue; |
| OffsetRegisterValue = IndirectAddress | BIT30; |
| GnbLibPciWrite (Address + 4, AccessWidth32, Value, Config); |
| GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); |
| do { |
| GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); |
| } while ((OffsetRegisterValue & BIT31) == 0); |
| } |
| |
| |