diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index a1cc45a..9a6c9cf 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -25,7 +25,6 @@
 #include <device/pci_ops.h>
 #include <arch/ioapic.h>
 #include <arch/acpi.h>
-#include "i82801gx.h"
 #include <cpu/x86/smm.h>
 #include <arch/acpigen.h>
 #include <arch/smp/mpspec.h>
@@ -33,6 +32,9 @@
 #include <string.h>
 #include <drivers/intel/gma/i915.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
+#include <southbridge/intel/common/pmbase.h>
+
+#include "i82801gx.h"
 #include "nvs.h"
 
 #define NMI_OFF	0
@@ -167,7 +169,7 @@
 static void i82801gx_power_options(struct device *dev)
 {
 	u8 reg8;
-	u16 reg16, pmbase;
+	u16 reg16;
 	u32 reg32;
 	const char *state;
 	/* Get the chip configuration */
@@ -254,18 +256,16 @@
 	// Set the board's GPI routing.
 	i82801gx_gpi_routing(dev);
 
-	pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
-
-	outl(config->gpe0_en, pmbase + GPE0_EN);
-	outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
+	write_pmbase32(GPE0_EN, config->gpe0_en);
+	write_pmbase16(ALT_GP_SMI_EN, config->alt_gp_smi_en);
 
 	/* Set up power management block and determine sleep mode */
-	reg32 = inl(pmbase + 0x04); // PM1_CNT
+	reg32 = read_pmbase32(PM1_CNT);
 
 	reg32 &= ~(7 << 10);	// SLP_TYP
 	reg32 |= (1 << 1);	// enable C3->C0 transition on bus master
 	reg32 |= (1 << 0);	// SCI_EN
-	outl(reg32, pmbase + 0x04);
+	write_pmbase32(PM1_CNT, reg32);
 }
 
 static void i82801gx_configure_cstates(struct device *dev)
@@ -486,15 +486,15 @@
 {
 	struct device *dev = pcidev_on_root(0x1f, 0);
 	config_t *chip = dev->chip_info;
-	u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+	u16 pmbase = lpc_get_pmbase();
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
 	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x20;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x28;
+	fadt->pm2_cnt_blk = pmbase + PM2_CNT;
+	fadt->pm_tmr_blk = pmbase + PM1_TMR;
+	fadt->gpe0_blk = pmbase + GPE0_STS;
 	fadt->gpe1_blk = 0;
 
 	fadt->pm1_evt_len = 4;
@@ -532,7 +532,7 @@
 	fadt->x_pm1a_cnt_blk.bit_width = 16;
 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
 	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
 
 	fadt->x_pm1b_cnt_blk.space_id = 0;
@@ -546,21 +546,21 @@
 	fadt->x_pm2_cnt_blk.bit_width = 8;
 	fadt->x_pm2_cnt_blk.bit_offset = 0;
 	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
-	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
 	fadt->x_pm2_cnt_blk.addrh = 0x0;
 
 	fadt->x_pm_tmr_blk.space_id = 1;
 	fadt->x_pm_tmr_blk.bit_width = 32;
 	fadt->x_pm_tmr_blk.bit_offset = 0;
 	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
 
 	fadt->x_gpe0_blk.space_id = 1;
 	fadt->x_gpe0_blk.bit_width = 64;
 	fadt->x_gpe0_blk.bit_offset = 0;
 	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
-	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
 	fadt->x_gpe0_blk.addrh = 0x0;
 
 	fadt->x_gpe1_blk.space_id = 0;