riscv-spike: Move coreboot to 0x80000000 (2GiB)
This is where the RAM is (now), on RISC-V.
We need to put coreboot.rom in RAM because Spike (at the moment) only
supports loading code into the RAM, not into the boot ROM.
Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld
index 276483f..8d35a64 100644
--- a/src/mainboard/emulation/spike-riscv/memlayout.ld
+++ b/src/mainboard/emulation/spike-riscv/memlayout.ld
@@ -17,12 +17,14 @@
#include <arch/header.ld>
+#define START 0x80000000
+
SECTIONS
{
- DRAM_START(0x0)
- BOOTBLOCK(0x0, 64K)
- STACK(8M, 64K)
- ROMSTAGE(8M + 64K, 128K)
- PRERAM_CBMEM_CONSOLE(8M + 192k, 8K)
- RAMSTAGE(8M + 200K, 256K)
+ DRAM_START(START)
+ BOOTBLOCK(START, 64K)
+ STACK(START + 8M, 64K)
+ ROMSTAGE(START + 8M + 64K, 128K)
+ PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
+ RAMSTAGE(START + 8M + 200K, 256K)
}