##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Google Inc.
## Copyright (C) 2015-2016 Intel Corp.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

chip soc/intel/quark

	############################################################
	# Set the parameters for MemoryInit
	############################################################

	register "PcdSmmTsegSize" = "0"	# SMM Region size in MiB

	############################################################
	# Enable the devices
	############################################################

	device domain 0 on
					# EDS Table 3
		device pci 00.0 on end	# 8086 0958 - Host Bridge
		device pci 14.0 on end	# 8086 08A7 - SD/SDIO/eMMC controller
		device pci 14.1 off end	# 8086 0936 - HSUART 0
		device pci 14.2 off end	# 8086 0939 - USB 2.0 Device port
		device pci 14.3 on end	# 8086 0939 - USB EHCI Host controller
		device pci 14.4 on end	# 8086 093A - USB OHCI Host controller
		device pci 14.5 on end	# 8086 0936 - HSUART 1
		device pci 14.6 off end	# 8086 0937 - 10/100 Ethernet MAC 0
		device pci 14.7 off end	# 8086 0937 - 10/100 Ethernet MAC 1
		device pci 15.0 off end	# 8086 0935 - SPI controller 0
		device pci 15.1 off end	# 8086 0935 - SPI controller 1
		device pci 15.2 off end	# 8086 0934 - I2C/GPIO controller
		device pci 17.0 on end	# 8086 11C3 - PCIe Root Port 0
		device pci 17.1 off end	# 8086 11C4 - PCIe Root Port 1
		device pci 1f.0 on end	# 8086 095E - Legacy Bridge
	end
end