mb/starlabs/labtop: Reconfigure CNVi GPIOs
Reconfigure the CNVi GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c
index 81de01e..559de8d 100644
--- a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c
@@ -279,15 +279,15 @@
/* F0: CNV_BRI_DT_BT_UART0_RTS_R */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
/* F1: CNV_BRI_RSP_BT_UART0_RX_R */
- PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
/* F2: CNV_RGI_DT_BT_UART0_TX_R */
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
/* F3: CNV_RGI_RSP_BT_UART0_CTS */
- PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
/* F4: Not Connected */
PAD_NC(GPP_F4, NONE),
/* F5: GPPC_F5_MODEM_CLKREQ */
- PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
+ PAD_NC(GPP_F5, NONE),
/* F6: Not Connected */
PAD_NC(GPP_F6, NONE),
/* F7: BIOS_REC */