| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * Config YANGTZE AB |
| * |
| * Init AB bridge. |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: FCH |
| * @e \$Revision: 87890 $ @e \$Date: 2013-02-12 13:09:22 -0600 (Tue, 12 Feb 2013) $ |
| * |
| */ |
| /* |
| ***************************************************************************** |
| * |
| * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * * Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * * Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| * its contributors may be used to endorse or promote products derived |
| * from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| **************************************************************************** |
| */ |
| #include "FchPlatform.h" |
| #include "Filecode.h" |
| #define FILECODE PROC_FCH_PCIE_FAMILY_YANGTZE_YANGTZEABENVSERVICE_FILECODE |
| |
| // |
| // Declaration of local functions |
| // |
| VOID AbCfgTbl (IN AB_TBL_ENTRY *ABTbl, IN AMD_CONFIG_PARAMS *StdHeader); |
| |
| /** |
| * YangtzeInitEnvAbTable - AB-Link Configuration Table for Yangtze |
| * |
| */ |
| AB_TBL_ENTRY YangtzeInitEnvAbTable[] = |
| { |
| // |
| // Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices. |
| // Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11) |
| // |
| {ABCFG, FCH_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18}, |
| |
| // |
| // Enabled SMI ordering enhancement. ABCFG 0x90[21] |
| // USB Delay A-Link Express L1 State. ABCFG 0x90[17] |
| // |
| {ABCFG, FCH_ABCFG_REG90, BIT21, BIT21}, |
| |
| // |
| // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1 |
| // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20] |
| // |
| {ABCFG, FCH_ABCFG_REG94, BIT20, BIT20 + 0x00FEE}, |
| |
| // |
| // Programming cycle delay for AB and BIF clock gating |
| // Enable the AB and BIF clock-gating logic. |
| // Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently |
| // |
| {ABCFG, FCH_ABCFG_REG10054, 0x00FFFFFF, 0x000007FF}, |
| {ABCFG, 0x98, 0x0003FF00, 0x00034700}, |
| |
| // |
| // Host Outstanding Completion Clock Gating |
| // |
| {ABCFG, 0x208, 0xFFFFFFEF, 0x00081000}, |
| |
| // |
| // SD ALink prefetch |
| // |
| {ABCFG, 0x10060ul, 0xFBFFFFFF, 0}, |
| |
| {ABCFG, FCH_ABCFG_REG10090, BIT16, BIT16}, |
| {ABCFG, 0, 0, (UINT8) 0xFF}, /// This dummy entry is to clear ab index |
| { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, |
| }; |
| |
| /** |
| * FchInitEnvAbLinkInit - Set ABCFG registers before PCI |
| * emulation. |
| * |
| * |
| * @param[in] FchDataPtr Fch configuration structure pointer. |
| * |
| */ |
| VOID |
| FchInitEnvAbLinkInit ( |
| IN VOID *FchDataPtr |
| ) |
| { |
| UINT16 AbTempVar; |
| UINT8 AbValue8; |
| AB_TBL_ENTRY *AbTblPtr; |
| FCH_DATA_BLOCK *LocalCfgPtr; |
| AMD_CONFIG_PARAMS *StdHeader; |
| |
| LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| StdHeader = LocalCfgPtr->StdHeader; |
| |
| // |
| // AB CFG programming |
| // |
| if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) { |
| RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT1, BIT1); |
| } else { |
| RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT1, 0); |
| } |
| |
| // |
| // Read Arbiter address, Arbiter address is in PMIO 6Ch |
| // |
| ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, &AbTempVar); |
| /// Write 0 to enable the arbiter |
| AbValue8 = 0; |
| LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader); |
| |
| AbTblPtr = (AB_TBL_ENTRY *) (&YangtzeInitEnvAbTable[0]); |
| AbCfgTbl (AbTblPtr, StdHeader); |
| |
| if ( LocalCfgPtr->Ab.ResetCpuOnSyncFlood ) { |
| RwAlink (0x10050ul | (UINT32) (ABCFG << 29), (UINT32)~BIT2, BIT2, StdHeader); |
| } |
| |
| if ( LocalCfgPtr->Ab.AbClockGating ) { |
| RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), (UINT32) (0x1 << 4), StdHeader); |
| RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader); |
| RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), (UINT32) (0x1 << 20), StdHeader); |
| RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 24), (UINT32) (0x3 << 24), StdHeader); |
| RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), (UINT32) (0x1 << 20), StdHeader); |
| } else { |
| RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), 0, StdHeader); |
| RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 24), 0, StdHeader); |
| RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), 0, StdHeader); |
| RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), 0, StdHeader); |
| RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), 0, StdHeader); |
| } |
| |
| if ( LocalCfgPtr->Ab.AbDmaMemoryWrtie3264B ) { |
| RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader); |
| RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) (0x1 << 2), StdHeader); |
| } else { |
| RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader); |
| RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) 0x0, StdHeader); |
| } |
| |
| if ( LocalCfgPtr->Ab.AbMemoryPowerSaving ) { |
| RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFB, 0x00); |
| RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 29), (UINT32) (0x1 << 29), StdHeader); |
| RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 31), (UINT32) (0x1 << 31), StdHeader); |
| } else { |
| RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x5 << 29), (UINT32) 0x0, StdHeader); |
| RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFB, 0x04); |
| } |
| |
| // |
| // A/B Clock Gate-OFF |
| // |
| if ( LocalCfgPtr->Ab.ALinkClkGateOff ) { |
| RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, BIT0); |
| } else { |
| RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, 0); |
| } |
| if ( LocalCfgPtr->Ab.BLinkClkGateOff ) { |
| RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, BIT1); |
| } else { |
| RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, 0); |
| } |
| if ( LocalCfgPtr->Ab.ALinkClkGateOff | LocalCfgPtr->Ab.BLinkClkGateOff ) { |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, BIT0); |
| } else { |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, 0); |
| } |
| |
| } |
| |
| /** |
| * AbCfgTbl - Program ABCFG by input table. |
| * |
| * |
| * @param[in] ABTbl ABCFG config table. |
| * @param[in] StdHeader |
| * |
| */ |
| VOID |
| AbCfgTbl ( |
| IN AB_TBL_ENTRY *ABTbl, |
| IN AMD_CONFIG_PARAMS *StdHeader |
| ) |
| { |
| UINT32 AbValue; |
| |
| while ( (ABTbl->RegType) != 0xFF ) { |
| if ( ABTbl->RegType == 0 ) { |
| AbValue = 0x30 | (ABTbl->RegType << 29); |
| WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader); |
| AbValue = 0x34 | (ABTbl->RegType << 29); |
| WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader); |
| } else if ( ABTbl->RegType == 2 ) { |
| AbValue = 0x38 | (ABTbl->RegType << 29); |
| WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader); |
| AbValue = 0x3C | (ABTbl->RegType << 29); |
| WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader); |
| } else { |
| AbValue = ABTbl->RegIndex | (ABTbl->RegType << 29); |
| WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader); |
| } |
| |
| ++ABTbl; |
| } |
| |
| // |
| //Clear ALink Access Index |
| // |
| AbValue = 0; |
| LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &AbValue, StdHeader); |
| } |
| |
| /** |
| * Is UMI One Lane GEN1 Mode? |
| * |
| * |
| * @retval TRUE or FALSE |
| * |
| */ |
| BOOLEAN |
| IsUmiOneLaneGen1Mode ( |
| IN AMD_CONFIG_PARAMS *StdHeader |
| ) |
| { |
| return (TRUE); |
| } |