| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * Config Fch HwAcpi controller |
| * |
| * Init HwAcpi Controller features (PEI phase). |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: FCH |
| * @e \$Revision: 87999 $ @e \$Date: 2013-02-14 10:48:03 -0600 (Thu, 14 Feb 2013) $ |
| * |
| */ |
| /* |
| ***************************************************************************** |
| * |
| * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * * Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * * Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| * its contributors may be used to endorse or promote products derived |
| * from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| **************************************************************************** |
| */ |
| #include "FchPlatform.h" |
| #include "Filecode.h" |
| #define FILECODE PROC_FCH_HWACPI_HWACPIRESET_FILECODE |
| |
| extern ACPI_REG_WRITE FchInitResetAcpiMmioTable[]; |
| |
| /** |
| * FchInitResetHwAcpiP - Config HwAcpi controller ( Preliminary |
| * ) during Power-On |
| * |
| * |
| * |
| * @param[in] FchDataPtr Fch configuration structure pointer. |
| * |
| */ |
| VOID |
| FchInitResetHwAcpiP ( |
| IN VOID *FchDataPtr |
| ) |
| { |
| FCH_RESET_DATA_BLOCK *LocalCfgPtr; |
| AMD_CONFIG_PARAMS *StdHeader; |
| |
| LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; |
| |
| StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; |
| |
| // |
| // Enabled (Mmio_mem_enable) |
| // |
| RwPmio (FCH_PMIOA_REG24, AccessWidth8, 0xFF, BIT0, StdHeader); |
| |
| ProgramFchHwAcpiResetP (FchDataPtr); |
| RwPmio (0xD2, AccessWidth8, (UINT32)~BIT6, 0, StdHeader); |
| } |
| |
| /** |
| * FchInitResetHwAcpi - Config HwAcpi controller during Power-On |
| * |
| * |
| * |
| * @param[in] FchDataPtr Fch configuration structure pointer. |
| * |
| */ |
| VOID |
| FchInitResetHwAcpi ( |
| IN VOID *FchDataPtr |
| ) |
| { |
| UINT16 SmbusBase; |
| UINT8 Value; |
| UINT16 AsfPort; |
| UINT32 GeventEnableBits; |
| UINT32 GeventValue; |
| FCH_RESET_DATA_BLOCK *LocalCfgPtr; |
| AMD_CONFIG_PARAMS *StdHeader; |
| |
| LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; |
| StdHeader = LocalCfgPtr->StdHeader; |
| |
| // |
| // Set Build option into SB |
| // |
| WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.FchBldCfg->CfgSioPmeBaseAddress), StdHeader); |
| |
| // |
| // Enabled SMBUS0/SMBUS1 (ASF) Base Address |
| // |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1] |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus1BaseAddress) + BIT0); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr)); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr)); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr)); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgCpuControlBlkAddr)); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr)); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr)); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr) + 8); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.FchBldCfg->CfgWatchDogTimerBase)); |
| |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, (UINT32)~(BIT1 + BIT2), 0); ///clear BIT[2:1] |
| SmbusBase = (UINT16) (UserOptions.FchBldCfg->CfgSmbus0BaseAddress); |
| Value = 0x00; |
| LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader); |
| |
| ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader); |
| |
| |
| if (UserOptions.FchBldCfg->CfgFchGpioControl != NULL) { |
| ProgramFchGpioTbl ((UserOptions.FchBldCfg->CfgFchGpioControl), LocalCfgPtr); |
| } |
| |
| if (UserOptions.FchBldCfg->CfgFchSataPhyControl != NULL) { |
| ProgramFchSataPhyTbl ((UserOptions.FchBldCfg->CfgFchSataPhyControl), LocalCfgPtr); |
| } |
| // |
| // RTC Workaround for Daylight saving time enable bit |
| // |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, BIT0 ); // Enable DltSavEnable |
| Value = 0x0B; |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); |
| LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); |
| Value &= 0xFE; |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0); |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, 0 ); // Disable DltSavEnable |
| // |
| // Prevent RTC error |
| // |
| Value = 0x0A; |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); |
| LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); |
| Value &= 0xEF; |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); |
| |
| Value = 0x08; |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); |
| LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); |
| |
| if ( !LocalCfgPtr->EcKbd ) { |
| // |
| // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input |
| // |
| Value = Value | 0x0A; |
| } |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); |
| |
| if ( UserOptions.FchBldCfg->CfgFchRtcWorkAround ) { |
| Value = RTC_WORKAROUND_SECOND; |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); |
| LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); |
| if ( Value > RTC_VALID_SECOND_VALUE ) { |
| Value = RTC_SECOND_RESET_VALUE; |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); |
| } |
| LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); |
| Value &= RTC_SECOND_LOWER_NIBBLE; |
| if ( Value > RTC_VALID_SECOND_VALUE_LN ) { |
| LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); |
| Value = RTC_SECOND_RESET_VALUE; |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); |
| } |
| } |
| |
| Value = 0x09; |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); |
| LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); |
| if ( !LocalCfgPtr->EcKbd ) { |
| // |
| // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input |
| // |
| Value = Value & 0xF9; |
| } |
| |
| if ( LocalCfgPtr->LegacyFree ) { |
| // |
| // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation. |
| // |
| Value = Value & 0x9F; |
| } |
| // |
| // Enabled IRQ input |
| // |
| Value = Value | BIT4; |
| LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); |
| |
| AsfPort = ((UINT16) UserOptions.FchBldCfg->CfgSmbus1BaseAddress & 0xFFF0); |
| if ( AsfPort != 0 ) { |
| UINT8 dbValue; |
| dbValue = 0x70; |
| LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader); |
| dbValue = 0x2F; |
| LibAmdIoWrite (AccessWidth8, AsfPort + 0x0A, &dbValue, StdHeader); |
| } |
| // |
| // PciExpWakeStatus workaround |
| // |
| ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort); |
| AsfPort++; |
| ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG04, AccessWidth32, &GeventEnableBits); |
| ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG00, AccessWidth32, &GeventValue); |
| if ( (GeventValue & GeventEnableBits) != 0 ) { |
| Value = 0x40; |
| LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader); |
| } |
| LibAmdIoRead (AccessWidth8, AsfPort, &Value, StdHeader); |
| if ((Value & (BIT2 + BIT0)) != 0) { |
| Value = 0x40; |
| LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader); |
| } |
| // |
| // Set ACPIMMIO by OEM Input table |
| // |
| if ( LocalCfgPtr->OemResetProgrammingTablePtr != NULL ) { |
| ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->OemResetProgrammingTablePtr), StdHeader); |
| } |
| } |
| |
| |