commit 702cf30e987ef07533ef589035d7256c0be3d52c
author Furquan Shaikh <furquan@google.com> Sat May 09 18:30:51 2020 -0700
committer Patrick Georgi <pgeorgi@google.com> Wed May 13 08:41:34 2020 +0000
tree c3eb22d6b450c5a11b116963304d7f441efe9cd4
parent ed8ceabf3e557bdaa104ebcab1cc98dc56b3536c

soc/amd/picasso: Enable eSPI capability for Picasso

This change selects SOC_AMD_COMMON_BLOCK_HAS_ESPI which enables
the capability for using eSPI on Picasso.

Additionally, it also calls espi_setup() and espi_configure_decodes()
if mainboard enables use of eSPI and skips LPC decodes in that case.

BUG=b:153675913,b:154445472

Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/picasso/Kconfig

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index ba44146..b065e2f 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -28,6 +28,7 @@
 	select UDELAY_TSC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK
+	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
 	select SOC_AMD_COMMON_BLOCK_IOMMU
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS

src/soc/amd/picasso/southbridge.c

diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 2df193a..2261a30 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -12,6 +12,7 @@
 #include <amdblocks/amd_pci_util.h>
 #include <amdblocks/reset.h>
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/espi.h>
 #include <amdblocks/lpc.h>
 #include <amdblocks/acpi.h>
 #include <amdblocks/spi.h>
@@ -202,13 +203,20 @@
 	asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
 }
 
+static void lpc_configure_decodes(void)
+{
+	if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
+		lpc_enable_port80();
+}
+
 /* Before console init */
 void fch_pre_init(void)
 {
 	lpc_early_init();
-	if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)
-					&& CONFIG(PICASSO_LPC_IOMUX))
-		lpc_enable_port80();
+
+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+		lpc_configure_decodes();
+
 	fch_spi_early_init();
 	enable_acpimmio_decode_pm04();
 	fch_smbus_init();
@@ -280,6 +288,11 @@
 
 	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
 		lpc_disable_spi_rom_sharing();
+
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
+		espi_setup();
+		espi_configure_decodes();
+	}
 }
 
 void sb_enable(struct device *dev)