diff --git a/src/arch/arm64/include/armv8/arch/barrier.h b/src/arch/arm64/include/armv8/arch/barrier.h
index 2be2bd3..00b9b62 100644
--- a/src/arch/arm64/include/armv8/arch/barrier.h
+++ b/src/arch/arm64/include/armv8/arch/barrier.h
@@ -24,7 +24,7 @@
 #define barrier() __asm__ __volatile__("" : : : "memory")
 #endif
 
-#define nop()		asm volatile("nop");
+#define nop()		asm volatile("nop")
 
 #define force_read(x) (*(volatile typeof(x) *)&(x))
 
diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h
index a859dfa..7d256b4 100644
--- a/src/include/cpu/intel/l2_cache.h
+++ b/src/include/cpu/intel/l2_cache.h
@@ -44,7 +44,7 @@
 #define BBLCR3_L2_SIZE_2M          (0x08 << 13)
 #define BBLCR3_L2_SIZE_4M          (0x10 << 13)
 /* bits [22:20] */
-#define BBLCR3_L2_PHYSICAL_RANGE   (0x7 << 20);
+#define BBLCR3_L2_PHYSICAL_RANGE   (0x7 << 20)
 /* TODO: This bitmask does not agree with Intel's documentation.
  * Get confirmation one way or another.
  */