cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZE
An epic battle to fix Nehalem finally ended when we found an odd mask
set in SMRR. This was caused by a wrong calculation of TSEG size. It
was assumed that TSEG spans the whole space between TSEG base
and GTT. This is wrong as TSEG base might have been aligned down.
TEST: On X201, copied 1GiB from usb key to sd-card and verified.
Change-Id: Id8c8a656446f092629fe2517f043e3c6d0f1b6b7
Found-by: Alexander Couzens, Nico Huber
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16939
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 53d93a2..a67b84d 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -500,16 +500,11 @@
return value;
}
-void
-northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size)
+u32 northbridge_get_tseg_base(void)
{
- device_t dev;
- u32 bgsm;
- dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
- *tsegmb = northbridge_get_base_reg(dev, TSEG);
- bgsm = northbridge_get_base_reg(dev, BGSM);
- *tseg_size = bgsm - *tsegmb;
+ return northbridge_get_base_reg(dev, TSEG);
}
void northbridge_write_smram(u8 smram)