tree 75e69d6b500ef33f32eaff750eb24c6f0496782e
parent fd46b497ead843eccfd80124ca8fbba7e57a3631
author Angel Pons <th3fanbus@gmail.com> 1631106416 +0200
committer Matt DeVillier <matt.devillier@gmail.com> 1713231965 +0000

sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask

Lynx Point PCH reference code version 1.9.1 masks the upper 4 bits of
the PCIe root port register at offset 0xf5.

Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57502
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>