sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask
Lynx Point PCH reference code version 1.9.1 masks the upper 4 bits of
the PCIe root port register at offset 0xf5.
Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57502
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index fd41ce8..30a34f7 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -662,7 +662,7 @@
/* Set Invalid Receive Range Check Enable in MPC register. */
pci_or_config32(dev, 0xd8, 1 << 25);
- pci_and_config8(dev, 0xf5, 0x3f);
+ pci_and_config8(dev, 0xf5, 0x0f);
if (rp == 1 || rp == 5 || (is_lp && rp == 6))
pci_and_config8(dev, 0xf7, ~0x0c);