mb/google/brask/variants/moli: Support DPTF oem_variables
Enable DPTF oem_variables and override based on CPU match id.
BUG=b:236294162
TEST=emerge-brask coreboot and check the value in odvp0 is correct.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ic935ec42f4de0cbec996da37b44f354978fe4b62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66907
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb
index 9f2c22b..e5a9a04 100644
--- a/src/mainboard/google/brya/variants/moli/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moli/overridetree.cb
@@ -88,6 +88,10 @@
}
}"
+ register "oem_data.oem_variables" = "{
+ [0] = 0x1
+ }"
+
## Fan Performance Control (Percent, Speed, Noise, Power)
register "controls.fan_perf" = "{
[0] = { 90, 6700, 220, 2200, },
diff --git a/src/mainboard/google/brya/variants/moli/ramstage.c b/src/mainboard/google/brya/variants/moli/ramstage.c
index 77bf3ae..ea863c5 100644
--- a/src/mainboard/google/brya/variants/moli/ramstage.c
+++ b/src/mainboard/google/brya/variants/moli/ramstage.c
@@ -5,10 +5,12 @@
#include <device/device.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include <device/pci.h>
#include <drivers/intel/gma/opregion.h>
#include <ec/google/chromeec/ec.h>
#include <fw_config.h>
#include <intelblocks/power_limit.h>
+#include <drivers/intel/dptf/chip.h>
const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
@@ -26,6 +28,35 @@
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 135 },
};
+static void update_oem_variables(void)
+{
+ struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+ uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
+ const struct device *policy_dev = DEV_PTR(dptf_policy);
+ struct drivers_intel_dptf_config *config = policy_dev->chip_info;
+
+ switch (mch_id) {
+ case PCI_DID_INTEL_ADL_P_ID_5:
+ config->oem_data.oem_variables[0] = 0;
+ break;
+
+ case PCI_DID_INTEL_ADL_P_ID_6:
+ config->oem_data.oem_variables[0] = 1;
+ break;
+
+ case PCI_DID_INTEL_ADL_P_ID_7:
+ config->oem_data.oem_variables[0] = 1;
+ break;
+
+ case PCI_DID_INTEL_ADL_P_ID_10:
+ config->oem_data.oem_variables[0] = 1;
+ break;
+
+ default:
+ config->oem_data.oem_variables[0] = 1;
+ }
+}
+
const struct psys_config psys_config = {
.efficiency = 97,
.psys_imax_ma = 11000,
@@ -37,4 +68,5 @@
size_t total_entries = ARRAY_SIZE(limits);
variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
variant_update_power_limits(limits, total_entries);
+ update_oem_variables();
}