tree 12abdbc765ede5f58d324e2fb4281189fb7078a6
parent e8feab018bb787d3dc54ec49f59ee6fb25bde3a6
author Raul E Rangel <rrangel@chromium.org> 1642797261 -0700
committer Felix Held <felix-coreboot@felixheld.de> 1643127219 +0000

lib/cbmem_console,console: Resurrect CONSOLE_CBMEM_DUMP_TO_UART

Chromebooks normally run with non-serial enabled firmware because
writing to the UART console is very slow. This unfortunately makes
debugging boot errors more difficult. We tend to rely on port 80s and/or
the vboot recovery code.

When CONSOLE_CBMEM_DUMP_TO_UART is selected it will dump the entire
cbmem console to the UART whenever `vboot_reboot()` is called. We don't
incur any boot time penalty in the happy path, but still retain the
ability to access the logs when an error occurs.

The previous implementation was using a hard coded UART index and
`get_uart_baudrate` was always returning 0 since `CONFIG_TTYS0_BAUD`
wasn't defined. This change makes it so the UART console properties are
available when CONSOLE_CBMEM_DUMP_TO_UART is set. This results in the
following .config diff:

    +CONFIG_UART_FOR_CONSOLE=0
    +CONFIG_TTYS0_BASE=0x3f8
    +CONFIG_TTYS0_LCS=3
    +CONFIG_CONSOLE_SERIAL_115200=y
    +CONFIG_TTYS0_BAUD=115200

This functionality is especially helpful on Guybrush. PSP Verstage is
run on S0i3 resume. Today, if there is an error, the cbmem console is
lost since it lives in the PSP SRAM.

BUG=b:213828947, b:215599230
TEST=Build non-serial guybrush FW and verify no serial output happens in
happy path. Inject a vboot error and perform an S0i3 suspend/resume.
Verify CBMEM console gets dumped to the correct UART.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I997942204603362e51876a9ae25e493fe527437b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>