soc/amd/cezanne: Add AMD Renoir SOC support
Add AMD SOC Family 17h Renoir CPUIDs per PPR doc #55922
Renoir is similar to Cezanne with only differences in CCX count.
Cezanne has one Zen3 CCX with 8 cores per CCX compared to
the two Zen2 CCX with 4 cores per CCX. Hence, coreboot side
Cezanne SOC code should be mostly compatible with Renoir and
can be leveraged.
Change-Id: I6b43eb782527351c79b835d094a5b61103cd6642
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83099
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index 2c3100f..4f39aef 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -24,6 +24,7 @@
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, CEZANNE_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
+ { X86_VENDOR_AMD, RENOIR_A1_CPUID, CPUID_ALL_STEPPINGS_MASK},
CPU_TABLE_END
};
diff --git a/src/soc/amd/cezanne/include/soc/cpu.h b/src/soc/amd/cezanne/include/soc/cpu.h
index 0239e19..1506420 100644
--- a/src/soc/amd/cezanne/include/soc/cpu.h
+++ b/src/soc/amd/cezanne/include/soc/cpu.h
@@ -4,6 +4,7 @@
#define AMD_CEZANNE_CPU_H
#define CEZANNE_A0_CPUID CPUID_FROM_FMS(0x19, 0x50, 0)
+#define RENOIR_A1_CPUID CPUID_FROM_FMS(0X17, 0X60, 1)
#define CEZANNE_VBIOS_VID_DID 0x10021638
#define BARCELO_VBIOS_VID_DID 0x100215e7