src/northbridge: Improve code formatting
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index af9a8bf..d48a089 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -35,7 +35,7 @@
for (i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0)
- printk(BIOS_DEBUG, "\n%02x:",i);
+ printk(BIOS_DEBUG, "\n%02x:",i);
val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %02x", val);
}
@@ -61,19 +61,19 @@
static inline void dump_pci_devices_on_bus(unsigned busn)
{
- device_t dev;
- for (dev = PCI_DEV(busn, 0, 0);
- dev <= PCI_DEV(busn, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- dump_pci_device(dev);
- }
+ device_t dev;
+ for (dev = PCI_DEV(busn, 0, 0);
+ dev <= PCI_DEV(busn, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ dump_pci_device(dev);
+ }
}
static inline void dump_spd_registers(const struct mem_controller *ctrl)
@@ -103,18 +103,18 @@
device = ctrl->channel1[i];
if (device) {
int j;
- printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
+ printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
for (j = 0; j < 128; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0)
- printk(BIOS_DEBUG, "\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
- printk(BIOS_DEBUG, "%02x ", byte);
+ printk(BIOS_DEBUG, "%02x ", byte);
}
printk(BIOS_DEBUG, "\n");
}
@@ -123,54 +123,53 @@
static inline void dump_smbus_registers(void)
{
unsigned device;
- printk(BIOS_DEBUG, "\n");
- for (device = 1; device < 0x80; device++) {
- int j;
+ printk(BIOS_DEBUG, "\n");
+ for (device = 1; device < 0x80; device++) {
+ int j;
if ( smbus_read_byte(device, 0) < 0 ) continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
- for (j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- status = smbus_read_byte(device, j);
- if (status < 0) {
+ for (j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
break;
- }
- if ((j & 0xf) == 0)
+ }
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
- byte = status & 0xff;
- printk(BIOS_DEBUG, "%02x ", byte);
- }
- printk(BIOS_DEBUG, "\n");
+ byte = status & 0xff;
+ printk(BIOS_DEBUG, "%02x ", byte);
+ }
+ printk(BIOS_DEBUG, "\n");
}
}
static inline void dump_io_resources(unsigned port)
{
-
int i;
printk(BIOS_DEBUG, "%04x:\n", port);
- for (i=0;i<256;i++) {
- uint8_t val;
- if ((i & 0x0f) == 0)
+ for (i=0;i<256;i++) {
+ uint8_t val;
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
- val = inb(port);
+ val = inb(port);
printk(BIOS_DEBUG, " %02x",val);
- if ((i & 0x0f) == 0x0f) {
- printk(BIOS_DEBUG, "\n");
- }
+ if ((i & 0x0f) == 0x0f) {
+ printk(BIOS_DEBUG, "\n");
+ }
port++;
- }
+ }
}
static inline void dump_mem(unsigned start, unsigned end)
{
- unsigned i;
+ unsigned i;
printk(BIOS_DEBUG, "dump_mem:");
- for (i=start;i<end;i++) {
+ for (i=start;i<end;i++) {
if ((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
- }
- printk(BIOS_DEBUG, "\n");
- }
+ }
+ printk(BIOS_DEBUG, "\n");
+}
#endif
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index 5296bdb..d4f77ae 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -23,9 +23,9 @@
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
- uint32_t pci_tolm;
+ uint32_t pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list);
+ pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
@@ -102,36 +102,36 @@
}
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(dev->link_list);
+ initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
}
struct chip_operations northbridge_intel_e7501_ops = {
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 4a3e993..71b19f6 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -12,16 +12,16 @@
unsigned long acpi_fill_mcfg(unsigned long current)
{
- /* Just a dummy */
- return current;
+ /* Just a dummy */
+ return current;
}
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
- uint32_t pci_tolm;
+ uint32_t pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list);
+ pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
@@ -108,37 +108,37 @@
};
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
.ops_pci = &intel_pci_ops,
.ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(dev->link_list);
+ initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
}
struct chip_operations northbridge_intel_e7505_ops = {
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 4af6e11..d4b6e90 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -101,8 +101,7 @@
/* There are special BARs that actually are programmed in the MCHBAR. These
* Intel special features, but they do consume resources that need to be
* accounted for. */
-static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
- u32 *len)
+static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, u32 *len)
{
u32 bar;
@@ -122,7 +121,7 @@
unsigned int index;
u32 size;
int (*get_resource)(device_t dev, unsigned int index,
- u32 *base, u32 *size);
+ u32 *base, u32 *size);
const char *description;
};
@@ -154,13 +153,13 @@
size = mc_fixed_resources[i].size;
index = mc_fixed_resources[i].index;
if (!mc_fixed_resources[i].get_resource(dev, index,
- &base, &size))
+ &base, &size))
continue;
resource = new_resource(dev, mc_fixed_resources[i].index);
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_RESERVE |
- IORESOURCE_ASSIGNED;
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED;
resource->base = base;
resource->size = size;
printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
@@ -198,8 +197,7 @@
const char *description;
};
-static void read_map_entry(device_t dev, struct map_entry *entry,
- uint64_t *result)
+static void read_map_entry(device_t dev, struct map_entry *entry, uint64_t *result)
{
uint64_t value;
uint64_t mask;
@@ -345,16 +343,16 @@
resource->base = mc_values[TSEG_REG];
resource->size = mc_values[BGSM_REG] - resource->base;
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_RESERVE |
- IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
/* BGSM -> TOLUD */
resource = new_resource(dev, index++);
resource->base = mc_values[BGSM_REG];
resource->size = mc_values[TOLUD_REG] - resource->base;
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_RESERVE |
- IORESOURCE_ASSIGNED;
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED;
/* 4GiB -> TOUUD */
base_k = 4096 * 1024; /* 4GiB */
@@ -370,7 +368,7 @@
*/
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
- (0x100000 - 0xc0000) >> 10);
+ (0x100000 - 0xc0000) >> 10);
#if CONFIG_CHROMEOS_RAMOOPS
reserved_ram_resource(dev, index++,
CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index c8e3221..a48d8fe 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -40,7 +40,7 @@
device_t mc_dev;
u32 pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list);
+ pci_tolm = find_pci_tolm(dev->link_list);
#if 1
printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
@@ -211,15 +211,15 @@
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(dev->link_list);
+ initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 497339c..001ec0d 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -618,7 +618,7 @@
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
- }
+ }
udelay(16);
/* No command */
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index a0bfd1b..1a802b0 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -599,7 +599,7 @@
val = (d->setup->t_al << 19) |
((odt & 1) << 18) |
- ((odt & 2) << 21) | 1;
+ ((odt & 2) << 21) | 1;
printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
@@ -1268,7 +1268,7 @@
mir0 = (size0 << 1) | 3;
mir1 = (size0 << 1);
mir2 = (size0 << 1);
- } else if (!size0) {
+ } else if (!size0) {
mir0 = size1 | 1;
mir1 = size1;
mir2 = size1;
diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c
index 05e934d..2a9e407 100644
--- a/src/northbridge/intel/i855/debug.c
+++ b/src/northbridge/intel/i855/debug.c
@@ -104,26 +104,26 @@
static inline void dump_smbus_registers(void)
{
- int i;
- printk(BIOS_DEBUG, "\n");
- for (i = 1; i < 0x80; i++) {
- unsigned device;
- device = i;
- int j;
- printk(BIOS_DEBUG, "smbus: %02x", device);
- for (j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0)
- printk(BIOS_DEBUG, "\n%02x: ", j);
- status = smbus_read_byte(device, j);
- if (status < 0) {
- printk(BIOS_DEBUG, "bad device\n");
- break;
- }
- byte = status & 0xff;
+ int i;
+ printk(BIOS_DEBUG, "\n");
+ for (i = 1; i < 0x80; i++) {
+ unsigned device;
+ device = i;
+ int j;
+ printk(BIOS_DEBUG, "smbus: %02x", device);
+ for (j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0)
+ printk(BIOS_DEBUG, "\n%02x: ", j);
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
+ printk(BIOS_DEBUG, "bad device\n");
+ break;
+ }
+ byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
- }
- printk(BIOS_DEBUG, "\n");
+ }
+ printk(BIOS_DEBUG, "\n");
}
}
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index e9b1cac..bc497a8 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -30,33 +30,33 @@
static void northbridge_init(device_t dev)
{
- printk(BIOS_SPEW, "Northbridge init\n");
+ printk(BIOS_SPEW, "Northbridge init\n");
}
static struct device_operations northbridge_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = northbridge_init,
- .enable = 0,
- .ops_pci = 0,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = northbridge_init,
+ .enable = 0,
+ .ops_pci = 0,
};
static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &northbridge_operations,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x3580,
+ .ops = &northbridge_operations,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x3580,
};
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
- uint32_t pci_tolm;
+ uint32_t pci_tolm;
- printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
+ printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device);
- pci_tolm = find_pci_tolm(dev->link_list);
+ pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children->sibling;
printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor);
printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device);
@@ -107,39 +107,39 @@
}
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
- .ops_pci_bus = pci_bus_default_ops,
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(dev->link_list);
+ initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
}
struct chip_operations northbridge_intel_i855_ops = {
- CHIP_NAME("Intel 855 Northbridge")
+ CHIP_NAME("Intel 855 Northbridge")
.enable_dev = enable_dev,
};
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index fe6059d..43400ab 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -369,32 +369,32 @@
PRINTK_DEBUG(" Sending RAM command 0x%08x\n", reg32);
pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32);
- // RAM_COMMAND_NORMAL is an exception.
- // It affects only the memory controller and does not need to be "sent" to the DIMMs.
+ // RAM_COMMAND_NORMAL is an exception.
+ // It affects only the memory controller and does not need to be "sent" to the DIMMs.
- if (command != RAM_COMMAND_NORMAL) {
+ if (command != RAM_COMMAND_NORMAL) {
- // Send the command to all DIMMs by accessing a memory location within each
- // NOTE: for mode select commands, some of the location address bits
- // are part of the command
+ // Send the command to all DIMMs by accessing a memory location within each
+ // NOTE: for mode select commands, some of the location address bits
+ // are part of the command
- // Map JEDEC mode bits to i855
- if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) {
+ // Map JEDEC mode bits to i855
+ if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) {
/* Host address lines [13:3] map to DIMM address lines [11, 9:0] */
i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9));
- }
+ }
- for (i = 0; i < (DIMM_SOCKETS * 2); ++i) {
- uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i);
- if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
+ for (i = 0; i < (DIMM_SOCKETS * 2); ++i) {
+ uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i);
+ if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
- uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
+ uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);
- read32((void *)(dimm_start_address + i855_mode_bits));
+ read32((void *)(dimm_start_address + i855_mode_bits));
- // Set the start of the next DIMM
- dimm_start_32M_multiple = dimm_end_32M_multiple;
- }
+ // Set the start of the next DIMM
+ dimm_start_32M_multiple = dimm_end_32M_multiple;
+ }
}
}
}
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 6228d63..946c984 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -78,21 +78,21 @@
void dump_spd_registers(void)
{
- unsigned device;
- device = DIMM0;
- while (device <= DIMM3) {
- int status = 0;
- int i;
- printk(BIOS_DEBUG, "\ndimm %02x", device);
+ unsigned device;
+ device = DIMM0;
+ while (device <= DIMM3) {
+ int status = 0;
+ int i;
+ printk(BIOS_DEBUG, "\ndimm %02x", device);
- for (i = 0; (i < 256) ; i++) {
- if ((i % 16) == 0) {
+ for (i = 0; (i < 256) ; i++) {
+ if ((i % 16) == 0) {
printk(BIOS_DEBUG, "\n%02x: ", i);
- }
+ }
status = smbus_read_byte(device, i);
- if (status < 0) {
- printk(BIOS_DEBUG, "bad device: %02x\n", -status);
- break;
+ if (status < 0) {
+ printk(BIOS_DEBUG, "bad device: %02x\n", -status);
+ break;
}
printk(BIOS_DEBUG, "%02x ", status);
}
@@ -103,13 +103,13 @@
void dump_mem(unsigned start, unsigned end)
{
- unsigned i;
+ unsigned i;
printk(BIOS_DEBUG, "dump_mem:");
- for (i=start;i<end;i++) {
+ for (i=start;i<end;i++) {
if ((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
- }
- printk(BIOS_DEBUG, "\n");
- }
+ }
+ printk(BIOS_DEBUG, "\n");
+}
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index 989f5ef..335e38a 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -46,31 +46,31 @@
#define PGETBL_ENABLED 0x1
#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
- ADPA_CRT_HOTPLUG_WARMUP_10MS | \
- ADPA_CRT_HOTPLUG_MONITOR_COLOR| \
- ADPA_CRT_HOTPLUG_SAMPLE_4S | \
- ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
- ADPA_CRT_HOTPLUG_VOLREF_325MV | \
- ADPA_CRT_HOTPLUG_ENABLE)
+ ADPA_CRT_HOTPLUG_WARMUP_10MS | \
+ ADPA_CRT_HOTPLUG_MONITOR_COLOR| \
+ ADPA_CRT_HOTPLUG_SAMPLE_4S | \
+ ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
+ ADPA_CRT_HOTPLUG_VOLREF_325MV | \
+ ADPA_CRT_HOTPLUG_ENABLE)
static struct resource *gtt_res = NULL;
static struct resource *mmio_res = NULL;
static int gtt_setup(u8 *mmiobase)
{
- u32 gttbase;
- device_t dev = dev_find_slot(0, PCI_DEVFN(0,0));
+ u32 gttbase;
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0,0));
- gttbase = pci_read_config32(dev, BGSM);
- printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase);
+ gttbase = pci_read_config32(dev, BGSM);
+ printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase);
- write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
- udelay(50);
- write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
+ write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
+ udelay(50);
+ write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
- write32(mmiobase + GFX_FLSH_CNTL, 0);
+ write32(mmiobase + GFX_FLSH_CNTL, 0);
- return 0;
+ return 0;
}
static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index ffad0d4..aa5db7d 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -289,29 +289,29 @@
};
enum ddr2_signals {
- CLKSET0 = 0,
- CTRL0,
- CLKSET1,
- CMD,
- CTRL1,
- CTRL2,
- CTRL3,
- DQS1,
- DQS2,
- DQS3,
- DQS4,
- DQS5,
- DQS6,
- DQS7,
- DQS8,
- DQ1,
- DQ2,
- DQ3,
- DQ4,
- DQ5,
- DQ6,
- DQ7,
- DQ8
+ CLKSET0 = 0,
+ CTRL0,
+ CLKSET1,
+ CMD,
+ CTRL1,
+ CTRL2,
+ CTRL3,
+ DQS1,
+ DQS2,
+ DQS3,
+ DQS4,
+ DQS5,
+ DQS6,
+ DQS7,
+ DQS8,
+ DQ1,
+ DQ2,
+ DQ3,
+ DQ4,
+ DQ5,
+ DQ6,
+ DQ7,
+ DQ8
};
#ifndef __BOOTBLOCK__