commit 6e368f79ecc42a60eb37b77535d35136afc2e106
author Jon Murphy <jpmurphy@google.com> Thu Feb 24 14:37:04 2022 -0700
committer Felix Held <felix-coreboot@felixheld.de> Mon Feb 28 13:29:24 2022 +0000
tree d6ba0d9ef48069df287eed311c24f67b192da574
parent 96bb0ba9e72297e98ecd2c2ce88cb4037d496ee5

soc/amd/sabrina: Add XHCI configuration

Add xhci 2 controller support for additional USB port/ Dummy setting

BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/soc/amd/sabrina/xhci.c

diff --git a/src/soc/amd/sabrina/xhci.c b/src/soc/amd/sabrina/xhci.c
index c95b5f9..c6c0545 100644
--- a/src/soc/amd/sabrina/xhci.c
+++ b/src/soc/amd/sabrina/xhci.c
@@ -6,6 +6,7 @@
 #include <amdblocks/smi.h>
 #include <bootstate.h>
 #include <device/device.h>
+#include <device/pci_ids.h>
 #include <drivers/usb/pci_xhci/pci_xhci.h>
 #include <soc/pci_devs.h>
 #include <soc/smi.h>
@@ -22,6 +23,12 @@
 		.gpe = GEVENT_31,
 		.direction = SMI_SCI_LVL_HIGH,
 		.level = SMI_SCI_EDG
+	},
+	{
+		.scimap = SMITYPE_XHC2_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
 	}
 };
 
@@ -30,25 +37,35 @@
 	if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
 		return CB_ERR_ARG;
 
-	if (dev->bus->dev->path.pci.devfn != PCIE_ABC_A_DEVFN)
-		return CB_ERR_ARG;
-
 	if (dev->path.type != DEVICE_PATH_PCI)
 		return CB_ERR_ARG;
 
-	if (dev->path.pci.devfn == XHCI0_DEVFN)
-		*gpe = xhci_sci_sources[0].gpe;
-	else if (dev->path.pci.devfn == XHCI1_DEVFN)
-		*gpe = xhci_sci_sources[1].gpe;
-	else
-		return CB_ERR_ARG;
+	if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
+		if (dev->path.pci.devfn == XHCI0_DEVFN) {
+			*gpe = xhci_sci_sources[0].gpe;
+			return CB_SUCCESS;
+		} else if (dev->path.pci.devfn == XHCI1_DEVFN) {
+			*gpe = xhci_sci_sources[1].gpe;
+			return CB_SUCCESS;
+		}
+	} else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) {
+		if (dev->path.pci.devfn == XHCI2_DEVFN
+		    && dev->device == PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI2) {
+			*gpe = xhci_sci_sources[2].gpe;
+			return CB_SUCCESS;
+		}
+	}
 
-	return CB_SUCCESS;
+	return CB_ERR_ARG;
 }
 
 static void configure_xhci_sci(void *unused)
 {
-	gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources));
+	const struct device *xhci_2 = DEV_PTR(xhci_2);
+	if (xhci_2->device == PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI2)
+		gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources));
+	else
+		gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources) - 1);
 }
 
 BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL);