src: Remove duplicated round up function
This removes CEIL_DIV and div_round_up() altogether and
replace it by DIV_ROUND_UP defined in commonlib/helpers.h.
Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 0b8c83f..cce1d69e 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -429,10 +429,10 @@
return -1;
}
- postdiv1 = div_round_up(VCO_MIN_KHZ, freq_khz);
+ postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
if (postdiv1 > max_postdiv1) {
- postdiv2 = div_round_up(postdiv1, max_postdiv1);
- postdiv1 = div_round_up(postdiv1, postdiv2);
+ postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
+ postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
}
vco_khz = freq_khz * postdiv1 * postdiv2;
@@ -605,9 +605,9 @@
apll_hz = apll_cfgs[freq]->freq;
rkclk_set_pll(pll_con, apll_cfgs[freq]);
- aclkm_div = div_round_up(apll_hz, ACLKM_CORE_HZ) - 1;
- pclk_dbg_div = div_round_up(apll_hz, PCLK_DBG_HZ) - 1;
- atclk_div = div_round_up(apll_hz, ATCLK_CORE_HZ) - 1;
+ aclkm_div = DIV_ROUND_UP(apll_hz, ACLKM_CORE_HZ) - 1;
+ pclk_dbg_div = DIV_ROUND_UP(apll_hz, PCLK_DBG_HZ) - 1;
+ atclk_div = DIV_ROUND_UP(apll_hz, ATCLK_CORE_HZ) - 1;
write32(&cru_ptr->clksel_con[con_base],
RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK <<
diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c
index 813746e..114b202 100644
--- a/src/soc/rockchip/rk3399/mipi.c
+++ b/src/soc/rockchip/rk3399/mipi.c
@@ -45,7 +45,7 @@
int two_frames;
unsigned int refresh = edid->mode.refresh;
- two_frames = div_round_up(MSECS_PER_SEC * 2, refresh);
+ two_frames = DIV_ROUND_UP(MSECS_PER_SEC * 2, refresh);
mdelay(two_frames);
}
@@ -158,7 +158,7 @@
static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi)
{
int i, vco, val;
- int lane_mbps = div_round_up(dsi->lane_bps, USECS_PER_SEC);
+ int lane_mbps = DIV_ROUND_UP(dsi->lane_bps, USECS_PER_SEC);
struct stopwatch sw;
vco = (lane_mbps < 200) ? 0 : (lane_mbps + 100) / 200;
@@ -318,7 +318,7 @@
fref = OSC_HZ;
/* constraint: 5Mhz <= Fref / N <= 40MHz */
- min_prediv = div_round_up(fref, 40 * MHz);
+ min_prediv = DIV_ROUND_UP(fref, 40 * MHz);
max_prediv = fref / (5 * MHz);
/* constraint: 80MHz <= Fvco <= 1500Mhz */
@@ -441,7 +441,7 @@
u64 lbcc_tmp;
lbcc_tmp = hcomponent * dsi->lane_bps / (8 * MSECS_PER_SEC);
- lbcc = div_round_up(lbcc_tmp, edid->mode.pixel_clock);
+ lbcc = DIV_ROUND_UP(lbcc_tmp, edid->mode.pixel_clock);
return lbcc;
}
@@ -532,7 +532,7 @@
* which is:
* (lane_mbps >> 3) / 20 > esc_clk_division
*/
- u32 esc_clk_division = div_round_up(dsi->lane_bps,
+ u32 esc_clk_division = DIV_ROUND_UP(dsi->lane_bps,
8 * 20 * USECS_PER_SEC);
write32(&dsi->mipi_regs->dsi_pwr_up, RESET);