diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index d067dc2..2d7965f 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -361,8 +361,6 @@
 	}
 }
 
-#define ROUNDUP_DIV(val, by) CEIL_DIV(val, by)
-#define ROUNDUP_DIV_THIS(val, by) val = ROUNDUP_DIV(val, by)
 static fsb_clock_t read_fsb_clock(void)
 {
 	switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) {
@@ -452,7 +450,7 @@
 		if (!clock)
 			die("Couldn't find compatible clock / CAS settings.\n");
 		tCKproposed = 8000 / clock;
-		CAS = ROUNDUP_DIV(tAAmin, tCKproposed);
+		CAS = DIV_ROUND_UP(tAAmin, tCKproposed);
 		printk(BIOS_SPEW, "Trying CAS %u, tCK %u.\n", CAS, tCKproposed);
 		for (; CAS <= DDR3_MAX_CAS; ++CAS)
 			if (cas_latencies & (1 << CAS))
@@ -488,10 +486,10 @@
 		if (spdinfo->channel[i].tWR > tWRmin)
 			tWRmin = spdinfo->channel[i].tWR;
 	}
-	ROUNDUP_DIV_THIS(tRASmin, tCLK);
-	ROUNDUP_DIV_THIS(tRPmin, tCLK);
-	ROUNDUP_DIV_THIS(tRCDmin, tCLK);
-	ROUNDUP_DIV_THIS(tWRmin, tCLK);
+	tRASmin = DIV_ROUND_UP(tRASmin, tCLK);
+	tRPmin = DIV_ROUND_UP(tRPmin, tCLK);
+	tRCDmin = DIV_ROUND_UP(tRCDmin, tCLK);
+	tWRmin = DIV_ROUND_UP(tWRmin, tCLK);
 
 	/* Lookup tRFC and calculate common tRFCmin. */
 	const unsigned int tRFC_from_clock_and_cap[][4] = {
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index d0dfb75..54ef278 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -602,7 +602,7 @@
 			break;
 		}
 	}
-	min_cas_latency = CEIL_DIV(cas_latency_time, cycletime);
+	min_cas_latency = DIV_ROUND_UP(cas_latency_time, cycletime);
 	cas_latency = 0;
 	while (supported_cas_latencies) {
 		cas_latency = find_highest_bit_set(supported_cas_latencies) + 3;
@@ -3231,7 +3231,7 @@
 
 static inline int div_roundup(int a, int b)
 {
-	return CEIL_DIV(a, b);
+	return DIV_ROUND_UP(a, b);
 }
 
 static unsigned lcm(unsigned a, unsigned b)
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index 1d05fa7..7acab31 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -572,7 +572,7 @@
 	printram("Selected DRAM frequency: %u MHz\n", val32);
 
 	/* Find CAS and CWL latencies */
-	val = CEIL_DIV(ctrl->tAA, ctrl->tCK);
+	val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
 	printram("Minimum  CAS latency   : %uT\n", val);
 	/* Find lowest supported CAS latency that satisfies the minimum value */
 	while (!((ctrl->cas_supported >> (val - 4)) & 1)
@@ -591,30 +591,30 @@
 	pci_write_config8(MCU, 0xc0, reg8);
 
 	/* Find tRCD */
-	val = CEIL_DIV(ctrl->tRCD, ctrl->tCK);
+	val = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
 	printram("Selected tRCD          : %uT\n", val);
 	reg8 = ((val - 4) & 0x7) << 4;
 	/* Find tRP */
-	val = CEIL_DIV(ctrl->tRP, ctrl->tCK);
+	val = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK);
 	printram("Selected tRP           : %uT\n", val);
 	reg8 |= ((val - 4) & 0x7);
 	pci_write_config8(MCU, 0xc1, reg8);
 
 	/* Find tRAS */
-	val = CEIL_DIV(ctrl->tRAS, ctrl->tCK);
+	val = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
 	printram("Selected tRAS          : %uT\n", val);
 	reg8 = ((val - 15) & 0x7) << 4;
 	/* Find tWR */
-	ctrl->WR = CEIL_DIV(ctrl->tWR, ctrl->tCK);
+	ctrl->WR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK);
 	printram("Selected tWR           : %uT\n", ctrl->WR);
 	reg8 |= ((ctrl->WR - 4) & 0x7);
 	pci_write_config8(MCU, 0xc2, reg8);
 
 	/* Find tFAW */
-	tFAW = CEIL_DIV(ctrl->tFAW, ctrl->tCK);
+	tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
 	printram("Selected tFAW          : %uT\n", tFAW);
 	/* Find tRRD */
-	tRRD = CEIL_DIV(ctrl->tRRD, ctrl->tCK);
+	tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
 	printram("Selected tRRD          : %uT\n", tRRD);
 	val = tFAW - 4 * tRRD;	/* number of cycles above 4*tRRD */
 	reg8 = ((val - 0) & 0x7) << 4;
@@ -622,11 +622,11 @@
 	pci_write_config8(MCU, 0xc3, reg8);
 
 	/* Find tRTP */
-	val = CEIL_DIV(ctrl->tRTP, ctrl->tCK);
+	val = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
 	printram("Selected tRTP          : %uT\n", val);
 	reg8 = ((val & 0x3) << 4);
 	/* Find tWTR */
-	val = CEIL_DIV(ctrl->tWTR, ctrl->tCK);
+	val = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
 	printram("Selected tWTR          : %uT\n", val);
 	reg8 |= ((val - 2) & 0x7);
 	pci_mod_config8(MCU, 0xc4, 0x3f, reg8);
@@ -639,7 +639,7 @@
 	 *     Since we previously set RxC4[7]
 	 */
 	reg8 = pci_read_config8(MCU, 0xc5);
-	val = CEIL_DIV(ctrl->tRFC, ctrl->tCK);
+	val = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
 	printram("Minimum  tRFC          : %uT\n", val);
 	if (val < 30) {
 		val = 0;
@@ -652,7 +652,7 @@
 	pci_write_config8(MCU, 0xc5, reg8);
 
 	/* Where does this go??? */
-	val = CEIL_DIV(ctrl->tRC, ctrl->tCK);
+	val = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK);
 	printram("Required tRC           : %uT\n", val);
 }