tree b9de747f9ae9be9dacb1999894dd3f3dd7839b87
parent d4f92fa603ee7156cb96cb4f1f5f2177b8323ee4
author Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> 1487979450 -0800
committer Martin Roth <martinroth@google.com> 1489140673 +0100

soc/intel/apollolake: Add PM methods to power gate SD card

This implements dynamic generation of sdcard GpioInt in SSDT.
GpioInt in SSDT generation is based on the card detect GPIO if
it is provided by the mainboard in devicetree.

This implements GNVS variable to store the address of sdcard cd pin.
GNVS used to store rxstate of the sdcard cd pin to get card presence.

Add _PS0/_PS3 methods to power gate the sd card controller in
S0ix and runtime PM.

CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should enter S0ix and resume with no issue.

Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18496
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>