soc/skylake/cpu: Fix Intel SpeedStep enable/disable
In an attempt at consolidation, commit 0a203d1  introduced
an additional read/write of the MISC_ENABLE msr, as well a bug
which nullified the setting of Intel SpeedStep by inserting said
read/write calls in between another set of read/write calls to the
same msr. Fix by reverting to previous (simpler) implementation.
 soc/intel/skylake: Use CPU common library code
Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify
SpeedStep bit correctly set based on devicetree setting.
Signed-off-by: Youness Alaoui <email@example.com>
Signed-off-by: Matt DeVillier <firstname.lastname@example.org>
Tested-by: build bot (Jenkins) <email@example.com>
Reviewed-by: Aaron Durbin <firstname.lastname@example.org>
1 file changed