soc/skylake/cpu: Fix Intel SpeedStep enable/disable

In an attempt at consolidation, commit 0a203d1 [1] introduced
an additional read/write of the MISC_ENABLE msr, as well a bug
which nullified the setting of Intel SpeedStep by inserting said
read/write calls in between another set of read/write calls to the
same msr.  Fix by reverting to previous (simpler) implementation.

[1] soc/intel/skylake: Use CPU common library code

Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify
SpeedStep bit correctly set based on devicetree setting.

Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9
Signed-off-by: Youness Alaoui <>
Signed-off-by: Matt DeVillier <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Aaron Durbin <>
1 file changed