soc/intel/cannonlake: Fix incorrect `prev_sleep_state` issue
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).
As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.
TEST=Able to build and boot google/hatch.
Without this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 5
With this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I05a2fab75c3d931651885db0003ab8c5748a1568
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71934
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 94725f6..512b49b 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -195,7 +195,7 @@
* S5 because the PCH does not set the WAK_STS bit when waking
* from a true G3 state.
*/
- if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
+ if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
prev_sleep_state = ACPI_S5;
/*