diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 594b09d..133ebee 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -24,6 +24,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include "pch.h"
+#include <pc80/mc146818rtc.h>
 
 typedef struct southbridge_intel_bd82x6x_config config_t;
 
@@ -45,6 +46,7 @@
 	u16 reg16;
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
+	u8 sata_mode;
 
 	printk(BIOS_DEBUG, "SATA: Initializing...\n");
 
@@ -53,48 +55,17 @@
 		return;
 	}
 
+	if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
+		/* Default to AHCI */
+		sata_mode = 0;
+
 	/* SATA configuration */
 
 	/* Enable BARs */
 	pci_write_config16(dev, PCI_COMMAND, 0x0007);
 
-	if (config->ide_legacy_combined) {
-		printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
-
-		/* No AHCI: clear AHCI base */
-		pci_write_config32(dev, 0x24, 0x00000000);
-		/* And without AHCI BAR no memory decoding */
-		reg16 = pci_read_config16(dev, PCI_COMMAND);
-		reg16 &= ~PCI_COMMAND_MEMORY;
-		pci_write_config16(dev, PCI_COMMAND, reg16);
-
-		pci_write_config8(dev, 0x09, 0x80);
-
-		/* Set timings */
-		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
-				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
-				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
-				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
-
-		/* Sync DMA */
-		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
-		pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
-
-		/* Set IDE I/O Configuration */
-		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
-		pci_write_config32(dev, IDE_CONFIG, reg32);
-
-		/* Port enable */
-		reg16 = pci_read_config16(dev, 0x92);
-		reg16 &= ~0x3f;
-		reg16 |= config->sata_port_map;
-		pci_write_config16(dev, 0x92, reg16);
-
-		/* SATA Initialization register */
-		pci_write_config32(dev, 0x94,
-			   ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
-	} else if(config->sata_ahci) {
+	/* AHCI */
+	if (sata_mode == 0) {
 		u32 abar;
 
 		printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -156,6 +127,7 @@
 		reg32 &= ~0x00000005;
 		write32(abar + 0xa0, reg32);
 	} else {
+	        /* IDE */
 		printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
 
 		/* No AHCI: clear AHCI base */
@@ -244,15 +216,19 @@
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 	u16 map = 0;
+	u8 sata_mode;
 
 	if (!config)
 		return;
 
+	if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
+		sata_mode = 0;
+
 	/*
 	 * Set SATA controller mode early so the resource allocator can
 	 * properly assign IO/Memory resources for the controller.
 	 */
-	if (config->sata_ahci)
+	if (sata_mode == 0)
 		map = 0x0060;
 
 	map |= (config->sata_port_map ^ 0x3f) << 8;