diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 0f11f63..a8e24cd 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -4,13 +4,13 @@
 		device lapic 0 on end
 	end
 
-	register "pcie_rp0_clkreq_pin" = "0"    # wifi/bt
+	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
 
 	# GPIO for PERST_0
 	# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
index 0a06c76..c1b7067 100644
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -4,13 +4,13 @@
 		device lapic 0 on end
 	end
 
-	register "pcie_rp0_clkreq_pin" = "0"    # wifi/bt
+	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
 
 	# GPIO for PERST_0
 	# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index 5bfe2c2..cb297d9 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -4,13 +4,13 @@
 		device lapic 0 on end
 	end
 
-	register "pcie_rp0_clkreq_pin" = "0"    # wifi/bt
+	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
 
 	# GPIO for PERST_0
 	# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index a6692e6..e53af88 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -4,13 +4,13 @@
 		device lapic 0 on end
 	end
 
-	register "pcie_rp0_clkreq_pin" = "0"    # wifi/bt
+	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
 
 	# GPIO for PERST_0
 	# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 6adf94c..9719368 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -4,13 +4,13 @@
 		device lapic 0 on end
 	end
 
-	register "pcie_rp0_clkreq_pin" = "0"    # wifi/bt
+	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
 
 	# GPIO for PERST_0
 	# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb
index 746aaf3..f7e82a0 100644
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@@ -1,11 +1,11 @@
 chip soc/intel/apollolake
 
-	register "pcie_rp0_clkreq_pin" = "2"	# PCIe slot 2
-	register "pcie_rp1_clkreq_pin" = "3"	# Wifi+BT M2 slot
-	register "pcie_rp2_clkreq_pin" = "0"	# PCIe slot 1
-	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[0]" = "2"	# PCIe slot 2
+	register "pcie_rp_clkreq_pin[1]" = "3"	# Wifi+BT M2 slot
+	register "pcie_rp_clkreq_pin[2]" = "0"	# PCIe slot 1
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index 45badcd..5a54430 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -4,13 +4,13 @@
 		device lapic 0 on end
 	end
 
-	register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
 	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp1_clkreq_pin" = "3" # wifi/bt
-	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp4_clkreq_pin" = "1"
-	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt
+	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]" = "1"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
 
 	# GPIO for PERST_0
 	# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
index 2a284d2..6c872b1 100644
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -1,11 +1,11 @@
 chip soc/intel/apollolake
 
-	register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end
diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb
index 2a284d2..6c872b1 100644
--- a/src/mainboard/intel/minnow3/devicetree.cb
+++ b/src/mainboard/intel/minnow3/devicetree.cb
@@ -1,11 +1,11 @@
 chip soc/intel/apollolake
 
-	register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end
diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb
index e2b6cee..c1ef76b 100644
--- a/src/mainboard/siemens/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/devicetree.cb
@@ -7,12 +7,12 @@
 	register "sci_irq" = "SCIS_IRQ10"
 
 	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge
-	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp2_clkreq_pin" = "0" # MACPHY
-	register "pcie_rp3_clkreq_pin" = "1" # MACPHY
-	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
+	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
+	register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
 
 	# EMMC TX DATA Delay 1
 	# Refer to EDS-Vol2-22.3.
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 53ffdb9..6006773 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -531,12 +531,8 @@
 	/* Parse device tree and disable unused device*/
 	parse_devicetree(silconfig);
 
-	silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
-	silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
-	silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
-	silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin;
-	silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
-	silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
+	memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin,
+	       sizeof(silconfig->PcieRpClkReqNumber));
 
 	if (cfg->emmc_tx_cmd_cntl != 0)
 		silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 8573cf4..7a1d16a 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -28,6 +28,7 @@
 #include <soc/pm.h>
 #include <soc/usb.h>
 
+#define MAX_PCIE_PORTS			6
 #define CLKREQ_DISABLED		0xf
 #define APOLLOLAKE_I2C_DEV_MAX	8
 
@@ -43,12 +44,7 @@
 	 * four CLKREQ inputs, but six root ports. Root ports without an
 	 * associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
 	 */
-	uint8_t pcie_rp0_clkreq_pin;
-	uint8_t pcie_rp1_clkreq_pin;
-	uint8_t pcie_rp2_clkreq_pin;
-	uint8_t pcie_rp3_clkreq_pin;
-	uint8_t pcie_rp4_clkreq_pin;
-	uint8_t pcie_rp5_clkreq_pin;
+	uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
 
 	/* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
 	 * [6:0] SDR mode Number of dealy elements.Each = 125pSec.