diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c
index c049d07..14aece3 100644
--- a/src/soc/intel/meteorlake/acpi.c
+++ b/src/soc/intel/meteorlake/acpi.c
@@ -167,6 +167,65 @@
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 }
 
+static struct min_sleep_state min_pci_sleep_states[] = {
+	{ SA_DEVFN_ROOT,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_IGD,		ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_DPTF,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_IPU,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_TBT0,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_TBT1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_TBT2,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_TBT3,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_GNA,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_TCSS_XHCI,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_TCSS_XDCI,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_TCSS_DMA0,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_TCSS_DMA1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_VMD,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_THC0,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_THC1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_XHCI,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_USBOTG,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_SRAM,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_CNVI_WIFI,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_I2C0,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_I2C1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_I2C2,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_I2C3,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_CSE,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_SATA,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_I2C4,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_I2C5,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_UART2,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_PCIE1,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE2,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE3,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE4,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE5,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE6,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE7,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE8,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE9,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE10,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE11,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_PCIE12,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_UART0,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_UART1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_GSPI0,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_GSPI1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_ESPI,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PMC,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_HDA,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_SPI,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_GBE,	ACPI_DEVICE_SLEEP_D3 },
+};
+
+struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size)
+{
+	*size = ARRAY_SIZE(min_pci_sleep_states);
+	return min_pci_sleep_states;
+}
+
 uint32_t soc_read_sci_irq_select(void)
 {
 	return read32p(soc_read_pmc_base() + IRQ_REG);