soc/amd/genoa: Add minimal viable code for compilation
This adds a dummy soc (genoa) based on EXAMPLE_MIN86 with
amd linker script hooked up.
Default to 64bit code as that will be a sensible default for this
platform (high memory access required for RAS setup).
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I69253466084d17c4359d7e824d69f12490b076e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76495
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
new file mode 100644
index 0000000..f799ac18
--- /dev/null
+++ b/src/soc/amd/genoa/Kconfig
@@ -0,0 +1,73 @@
+config SOC_AMD_GENOA
+ bool
+
+if SOC_AMD_GENOA
+
+config SOC_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select HAVE_EXP_X86_64_SUPPORT
+ select NO_ECAM_MMCONF_SUPPORT
+ select NO_MONOTONIC_TIMER
+ select RESET_VECTOR_IN_RAM
+ select SOC_AMD_COMMON
+ select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+ select SOC_AMD_COMMON_BLOCK_NONCAR
+ select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+ select UNKNOWN_TSC_RATE
+
+config USE_EXP_X86_64_SUPPORT
+ default y
+
+config EARLY_RESERVED_DRAM_BASE
+ hex
+ default 0x7000000
+ help
+ This variable defines the base address of the DRAM which is reserved
+ for usage by coreboot in early stages (i.e. before ramstage is up).
+ This memory gets reserved in BIOS tables to ensure that the OS does
+ not use it, thus preventing corruption of OS memory in case of S3
+ resume.
+
+config EARLYRAM_BSP_STACK_SIZE
+ hex
+ default 0x1000
+
+config PSP_APOB_DRAM_ADDRESS
+ hex
+ default 0x7001000
+ help
+ Location in DRAM where the PSP will copy the AGESA PSP Output
+ Block.
+
+config PSP_APOB_DRAM_SIZE
+ hex
+ default 0x20000
+
+config PRERAM_CBMEM_CONSOLE_SIZE
+ hex
+ default 0x1600
+ help
+ Increase this value if preram cbmem console is getting truncated
+
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x10000
+ help
+ Sets the size of the bootblock stage that should be loaded in DRAM.
+ This variable controls the DRAM allocation size in linker script
+ for bootblock stage.
+
+config ROMSTAGE_ADDR
+ hex
+ default 0x7040000
+ help
+ Sets the address in DRAM where romstage should be loaded.
+
+config ROMSTAGE_SIZE
+ hex
+ default 0x80000
+ help
+ Sets the size of DRAM allocation for romstage in linker script.
+
+endif
diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc
new file mode 100644
index 0000000..01b1965
--- /dev/null
+++ b/src/soc/amd/genoa/Makefile.inc
@@ -0,0 +1,13 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ifeq ($(CONFIG_SOC_AMD_GENOA),y)
+
+bootblock-y += early_fch.c
+
+romstage-y += romstage.c
+
+ramstage-y += chip.c
+ramstage-y += timer.c
+
+CPPFLAGS_common += -I$(src)/soc/amd/genoa/include
+
+endif
diff --git a/src/soc/amd/genoa/chip.c b/src/soc/amd/genoa/chip.c
new file mode 100644
index 0000000..cbe3e13
--- /dev/null
+++ b/src/soc/amd/genoa/chip.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+struct chip_operations soc_amd_genoa_ops = { NULL };
diff --git a/src/soc/amd/genoa/early_fch.c b/src/soc/amd/genoa/early_fch.c
new file mode 100644
index 0000000..dcb390b
--- /dev/null
+++ b/src/soc/amd/genoa/early_fch.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/espi.h>
+#include <amdblocks/lpc.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/aoac.h>
+#include <amdblocks/pmlib.h>
+#include <amdblocks/uart.h>
+#include <soc/southbridge.h>
+
+/* Before console init */
+void fch_pre_init(void)
+{
+
+}
+
+/* After console init */
+void fch_early_init(void)
+{
+
+}
diff --git a/src/soc/amd/genoa/include/soc/iomap.h b/src/soc/amd/genoa/include/soc/iomap.h
new file mode 100644
index 0000000..076938e
--- /dev/null
+++ b/src/soc/amd/genoa/include/soc/iomap.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_GENOA_IOMAP_H
+#define AMD_GENOA_IOMAP_H
+
+#define SPI_BASE_ADDRESS 0xfec10000
+
+/* @Todo : Check these values for Genoa */
+
+/* I/O Ranges */
+#define ACPI_IO_BASE 0x0400
+#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10)
+
+/* FCH AL2AHB Registers */
+#define ALINK_AHB_ADDRESS 0xfedc0000
+
+#define APU_I2C0_BASE 0xfedc2000
+#define APU_I2C1_BASE 0xfedc3000
+#define APU_I2C2_BASE 0xfedc4000
+#define APU_I2C3_BASE 0xfedc5000
+
+#define APU_UART0_BASE 0xfedc9000
+#define APU_UART1_BASE 0xfedca000
+#define APU_UART2_BASE 0xfedce000
+
+#endif /* AMD_GENOA_IOMAP_H */
diff --git a/src/soc/amd/genoa/include/soc/southbridge.h b/src/soc/amd/genoa/include/soc/southbridge.h
new file mode 100644
index 0000000..95c054c
--- /dev/null
+++ b/src/soc/amd/genoa/include/soc/southbridge.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_GENOA_SOUTHBRIDGE_H
+#define AMD_GENOA_SOUTHBRIDGE_H
+
+#include <soc/iomap.h>
+
+
+void fch_pre_init(void);
+void fch_early_init(void);
+
+#endif /* AMD_GENOA_SOUTHBRIDGE_H */
diff --git a/src/soc/amd/genoa/romstage.c b/src/soc/amd/genoa/romstage.c
new file mode 100644
index 0000000..f4c5584
--- /dev/null
+++ b/src/soc/amd/genoa/romstage.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <romstage_common.h>
+#include <halt.h>
+
+void __noreturn romstage_main(void)
+{
+ /* Needed for __noreturn */
+ halt();
+}
diff --git a/src/soc/amd/genoa/timer.c b/src/soc/amd/genoa/timer.c
new file mode 100644
index 0000000..9054ffd
--- /dev/null
+++ b/src/soc/amd/genoa/timer.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <delay.h>
+
+void init_timer(void)
+{
+}