tree e3940009f00f31d947ca0c12681effa5d911b8dd
parent dbcf7b16219df0c04401b8fcd6a780174a7df305
author Tim Wawrzynczak <twawrzynczak@chromium.org> 1589410833 -0600
committer Patrick Georgi <pgeorgi@google.com> 1589968140 +0000

soc/intel/tigerlake: Move PMC PCI resources under PMC device

Historically in coreboot, the PMC's fixed PCI resources were described
by the System Agent (the MMIO resource), and eSPI/LPC (the I/O
resource). This patch moves both of those to a new Intel SoC-specific
function, soc_pmc_read_resources(). On TGL, this new function takes care
of providing the MMIO and I/O resources for the PMC.

BUG=b:156388055
TEST=verified on volteer that the resource allocator is aware of and
does not touch these two resources:
("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0
	flags f0000200 index 0
  PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff
	flags c0000100 index 1")

Also verify that the MEM resource is described in the coreboot table:
("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved")

Verified the memory range is also untouchable from Linux:
("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved")

Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>