soc/intel/tigerlake: Move PMC PCI resources under PMC device
Historically in coreboot, the PMC's fixed PCI resources were described
by the System Agent (the MMIO resource), and eSPI/LPC (the I/O
resource). This patch moves both of those to a new Intel SoC-specific
function, soc_pmc_read_resources(). On TGL, this new function takes care
of providing the MMIO and I/O resources for the PMC.
BUG=b:156388055
TEST=verified on volteer that the resource allocator is aware of and
does not touch these two resources:
("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0
flags f0000200 index 0
PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff
flags c0000100 index 1")
Also verify that the MEM resource is described in the coreboot table:
("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved")
Verified the memory range is also untouchable from Linux:
("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved")
Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
index 7350319..8d847f7 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
@@ -305,7 +305,7 @@
end
end # eSPI
device pci 1f.1 off end # P2SB
- device pci 1f.2 on end # PMC
+ device pci 1f.2 hidden end # PMC
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI Flash Controller
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index fa99de8..5d5dcc4 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -370,7 +370,7 @@
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
device spi 0 on end
end
- end # GSPI0 0xA0AA
+ end # GSPI0 0xA0AA
device pci 1e.3 on
chip drivers/spi/acpi
register "name" = ""CRFP""
@@ -380,14 +380,14 @@
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)"
device spi 0 on end
end # FPMCU
- end # GSPI1 0xA0AB
+ end # GSPI1 0xA0AB
device pci 1f.0 on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
- end # eSPI 0xA080 - A09F
+ end # eSPI 0xA080 - A09F
device pci 1f.1 off end # P2SB 0xA0A0
- device pci 1f.2 on end # PMC 0xA0A1
+ device pci 1f.2 hidden end # PMC 0xA0A1
device pci 1f.3 on
chip drivers/generic/max98357a
register "hid" = ""MX98357A""
@@ -395,7 +395,7 @@
register "sdmode_delay" = "5"
device generic 0 on end
end
- end # Intel HD audio 0xA0C8-A0CF
+ end # Intel HD audio 0xA0C8-A0CF
device pci 1f.4 off end # SMBus 0xA0A3
device pci 1f.5 on end # SPI 0xA0A4
device pci 1f.6 off end # GbE 0x15E1/0x15E2
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 82f358e..045dc89 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -243,7 +243,7 @@
device pci 1e.3 off end # GSPI1 0xA0AB
device pci 1f.0 on end # eSPI 0xA080 - A09F
device pci 1f.1 on end # P2SB 0xA0A0
- device pci 1f.2 on end # PMC 0xA0A1
+ device pci 1f.2 hidden end # PMC 0xA0A1
device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
device pci 1f.4 on end # SMBus 0xA0A3
device pci 1f.5 on end # SPI 0xA0A4
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index fec2fef..83b6c0a 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -239,7 +239,7 @@
device pci 1e.3 off end # GSPI1 0xA0AB
device pci 1f.0 on end # eSPI 0xA080 - A09F
device pci 1f.1 on end # P2SB 0xA0A0
- device pci 1f.2 on end # PMC 0xA0A1
+ device pci 1f.2 hidden end # PMC 0xA0A1
device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
device pci 1f.4 on end # SMBus 0xA0A3
device pci 1f.5 on end # SPI 0xA0A4
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index c1764cd..a923074 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <fsp/api.h>
@@ -151,11 +152,17 @@
static void soc_enable(struct device *dev)
{
- /* Set the operations if it is a special bus type */
+ /*
+ * Set the operations if it is a special bus type or a hidden PCI
+ * device.
+ */
if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops;
+ else if (dev->path.type == DEVICE_PATH_PCI &&
+ dev->path.pci.devfn == PCH_DEVFN_PMC)
+ dev->ops = &pmc_ops;
}
struct chip_operations soc_intel_tigerlake_ops = {
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
index ed8481a..8cc8303 100644
--- a/src/soc/intel/tigerlake/espi.c
+++ b/src/soc/intel/tigerlake/espi.c
@@ -197,21 +197,4 @@
soc_mirror_dmi_pcr_io_dec();
}
-/* Fill up ESPI IO resource structure inside SoC directory */
-void pch_lpc_soc_fill_io_resources(struct device *dev)
-{
- /*
- * PMC pci device gets hidden from PCI bus due to Silicon
- * policy hence bind ACPI BASE aka ABASE (offset 0x20) with
- * ESPI IO resources to ensure that ABASE falls under PCI reserved
- * IO memory range.
- *
- * Note: Don't add any more resource with same offset 0x20
- * under this device space.
- */
- pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4,
- ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
-}
-
#endif
diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h
index 3b58a74..0f72833 100644
--- a/src/soc/intel/tigerlake/include/soc/pmc.h
+++ b/src/soc/intel/tigerlake/include/soc/pmc.h
@@ -3,6 +3,10 @@
#ifndef _SOC_TIGERLAKE_PMC_H_
#define _SOC_TIGERLAKE_PMC_H_
+#include <device/device.h>
+
+extern struct device_operations pmc_ops;
+
/* PCI Configuration Space (D31:F2): PMC */
#define PWRMBASE 0x10
#define ABASE 0x20
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index 136f103..fa59d46 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -75,7 +75,7 @@
write32(pmcbase + DSX_CFG, reg);
}
-static void pmc_init(void *unused)
+static void pmc_init(struct device *dev)
{
const config_t *config = config_of_soc();
@@ -91,11 +91,24 @@
config_deep_sx(config->deep_sx_config);
}
-/*
-* Initialize PMC controller.
-*
-* PMC controller gets hidden from PCI bus during FSP-Silicon init call.
-* Hence PCI enumeration can't be used to initialize bus device and
-* allocate resources.
-*/
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL);
+static void soc_pmc_read_resources(struct device *dev)
+{
+ struct resource *res;
+
+ /* Add the fixed MMIO resource */
+ mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
+
+ /* Add the fixed I/O resource */
+ res = new_resource(dev, 1);
+ res->base = (resource_t)ACPI_BASE_ADDRESS;
+ res->size = (resource_t)ACPI_BASE_SIZE;
+ res->limit = res->base + res->size - 1;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+struct device_operations pmc_ops = {
+ .read_resources = soc_pmc_read_resources,
+ .set_resources = noop_set_resources,
+ .enable = pmc_init,
+ .scan_bus = scan_static_bus,
+};
diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c
index 977c667..8c0a42a 100644
--- a/src/soc/intel/tigerlake/systemagent.c
+++ b/src/soc/intel/tigerlake/systemagent.c
@@ -32,17 +32,6 @@
{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
- /*
- * PMC pci device gets hidden from PCI bus due to Silicon
- * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with
- * SA resources to ensure that PMCBAR falls under PCI reserved
- * memory range.
- *
- * Note: Don't add any more resource with same offset 0x10
- * under this device space.
- */
- { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE,
- "PMCBAR" },
};
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,