commit 6ccb252918c8a076dcf0a122e3aac028b4e80d4e
author Angel Pons <th3fanbus@gmail.com> Sun Jun 13 11:24:11 2021 +0200
committer Patrick Georgi <pgeorgi@google.com> Tue Jun 15 07:45:59 2021 +0000
tree e4db54c6dded9c23e5590d7d328ad3b9f8410c27
parent d1fca8f7f7432d5c3fe59f59f6373d147a82104c

cpu/intel/msr.h: Sort MSRs in ascending order

Sort MSR definitions in ascending order to keep things organized.

Change-Id: Iadfd28014dc6f41dae7b52b1550c699c89fe8bdc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

src/include/cpu/intel/msr.h

diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h
index 9d2b62f..097ddb6 100644
--- a/src/include/cpu/intel/msr.h
+++ b/src/include/cpu/intel/msr.h
@@ -7,10 +7,6 @@
  * Common MSRs for Intel CPUs
  */
 
-#define MSR_FEATURE_CONFIG	0x13c
-#define  AESNI_DISABLE		(1 << 1)
-#define  AESNI_LOCK		(1 << 0)
-
 #define MSR_PIC_MSG_CONTROL	0x2e
 #define  TPR_UPDATES_DISABLE	(1 << 10)
 
@@ -26,6 +22,10 @@
 #define  B_BOOT_GUARD_SACM_INFO_BTG_CAPABILITY	(1ull << 32)
 #define  B_BOOT_GUARD_SACM_INFO_TXT_CAPABILITY	(1ull << 34)
 
+#define MSR_FEATURE_CONFIG	0x13c
+#define  AESNI_DISABLE		(1 << 1)
+#define  AESNI_LOCK		(1 << 0)
+
 #define MSR_PKG_C10_RESIDENCY	0x632
 
 #endif /* CPU_INTEL_MSR_H */