mb/google/dedede/var/storo: Set the xHCI LFPS period sampling off time to 0ms
LTE module L850-GL may encounter U3 wakeup race condition with the host.
Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not
miss the device-initiated U3 wakeup thus avoid the race condition.
BUG=b:193898133
BRANCH=dedede
TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ic84dc83b749cf3c6029a06730096b64ef8cb8cd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index e824652..aedb285 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -79,6 +79,8 @@
register "tcc_offset" = "10" # TCC of 95C
+ register "xhci_lfps_sampling_offtime_ms" = "0"
+
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf