skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index dd2fc60..d6bc990 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -125,24 +125,6 @@
register "PcieRpClkSrcNumber[10]" = "3"
register "PcieRpClkSrcNumber[11]" = "3"
- register "usb2_ports" = "{
- [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
- [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
- [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */
- [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
- [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
- [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
- [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
- [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */
- }"
-
- register "usb3_ports" = "{
- [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
- [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
- [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
- [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
- }"
-
# PL2 override 25W
register "power_limits_config" = "{
.tdp_pl2_override = 25,
@@ -154,7 +136,25 @@
device domain 0 on
device ref igpu on end
device ref sa_thermal on end
- device ref south_xhci on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
+ [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
+ [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */
+ [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
+ [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
+ [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
+ [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
+ [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
+ }"
+ end
device ref south_xdci on end
device ref thermal on end
device ref heci1 on end