skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index d64a9f9..a6ec6b6 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -233,22 +233,6 @@
# RP 12 uses CLK SRC 2
register "PcieRpClkSrcNumber[11]" = "2"
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C
- register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear
- register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front
- register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front
- register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear
- register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
- register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
-
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug
@@ -306,6 +290,25 @@
device ref igpu on end
device ref sa_thermal on end
device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_LONG(OC0), // Type-C
+ [1] = USB2_PORT_MID(OC3), // Type-A Rear
+ [2] = USB2_PORT_MID(OC2), // Type-A Front
+ [3] = USB2_PORT_MID(OC2), // Type-A Front
+ [4] = USB2_PORT_MID(OC1), // Type-A Rear
+ [5] = USB2_PORT_MID(OC1), // Type-A Rear
+ [6] = USB2_PORT_MID(OC_SKIP), // Bluetooth
+ [7] = USB2_PORT_MID(OC_SKIP), // Type-A 2.0 / Debug
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), // Type-C
+ [1] = USB3_PORT_DEFAULT(OC3), // Type-A Rear
+ [2] = USB3_PORT_DEFAULT(OC2), // Type-A Front
+ [3] = USB3_PORT_DEFAULT(OC2), // Type-A Front
+ [4] = USB3_PORT_DEFAULT(OC1), // Type-A Rear
+ [5] = USB3_PORT_DEFAULT(OC1), // Type-A Rear
+ }"
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"