device/dram/ddr4.h: Align with DDR3 and DDR2
Drop unnecessary typedefs and rename DDR4-specific definitions to avoid
name clashes, as done for DDR3 in earlier commits. This allows including
and using both DDR3 and DDR4 headers in the same compilation unit.
Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c
index e670b20..cc66dcc 100644
--- a/src/device/dram/ddr4.c
+++ b/src/device/dram/ddr4.c
@@ -163,7 +163,7 @@
* SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD
* SPD_STATUS_CRC_ERROR -- checksum mismatch
*/
-int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd)
+int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd)
{
u8 reg8;
u8 bus_width, sdram_width;
@@ -261,7 +261,7 @@
}
enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq,
- const dimm_attr *info)
+ const struct dimm_attr_ddr4_st *info)
{
struct memory_info *mem_info;
struct dimm_info *dimm;
@@ -298,16 +298,16 @@
dimm->mod_id = info->manufacturer_id;
switch (info->dimm_type) {
- case SPD_DIMM_TYPE_SO_DIMM:
+ case SPD_DDR4_DIMM_TYPE_SO_DIMM:
dimm->mod_type = SPD_SODIMM;
break;
- case SPD_DIMM_TYPE_72B_SO_RDIMM:
+ case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM:
dimm->mod_type = SPD_72B_SO_RDIMM;
break;
- case SPD_DIMM_TYPE_UDIMM:
+ case SPD_DDR4_DIMM_TYPE_UDIMM:
dimm->mod_type = SPD_UDIMM;
break;
- case SPD_DIMM_TYPE_RDIMM:
+ case SPD_DDR4_DIMM_TYPE_RDIMM:
dimm->mod_type = SPD_RDIMM;
break;
default: