mb/intel/adlrvp: x4 slot support (SD card support) for Adl-P RVP
Use clock src and clock req to 7 for x4 slot.
Remove free running clock setting for clock 6.
Configure gpio for source clock OEB native function going to x4 slot.
BUG=b:233252409
BRANCH=firmware-brya-14505.B
TEST=insert SD AIC to x4 slot. boot to OS and use 'lspci' to check
the device.
ex:
58:00.0 SD Host controller: O2 Micro, Inc. Device 8621 (rev 01)
NOTE: The bus number varies.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Iba5d83d133b6ae8cd389ddd971db308170094300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 8847d88..df4ac60 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -52,12 +52,14 @@
.flags = PCIE_RP_CLK_REQ_DETECT,
}"
- # Enable PCH PCIE RP 8 using free running CLK (0x80)
- # Clock source is shared with LAN and hence marked as free running.
+ # NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7
register "pch_pcie_rp[PCH_RP(8)]" = "{
- .flags = PCIE_RP_CLK_SRC_UNUSED,
+ .clk_src = 7,
+ .clk_req = 7,
+ .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+ .PcieRpL1Substates = L1_SS_L1_2,
+ .pcie_rp_detect_timeout_ms = 50,
}"
- register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
# Enable PCH PCIE RP 9 using CLK 1
register "pch_pcie_rp[PCH_RP(9)]" = "{
diff --git a/src/mainboard/intel/adlrvp/early_gpio.c b/src/mainboard/intel/adlrvp/early_gpio.c
index 57cadfa..af933eb 100644
--- a/src/mainboard/intel/adlrvp/early_gpio.c
+++ b/src/mainboard/intel/adlrvp/early_gpio.c
@@ -18,6 +18,15 @@
/* EC_IN_RW */
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+ /* x4 PCIE slot 1 RESET */
+ PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+
+ /* Support external source clock via OEB6 and OEB7 */
+ /* SRCCLK_OEB6 for built-in LAN */
+ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF2),
+ /* SRCCLK_OEB7 for x4 slot */
+ PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1),
+
/* CPU PCIe VGPIO for RP0 */
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, PLTRST, NF1),
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 92a8c30..e4483d2 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -67,10 +67,6 @@
PAD_CFG_GPO(GPP_B4, 1, PLTRST),
/* M.2_PCH_SSD_PWREN */
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
- /* SRCCLK_OEB7 */
- PAD_CFG_GPO(GPP_A7, 0, PLTRST),
- /* SRCCLK_OEB6 */
- PAD_CFG_GPO(GPP_E5, 0, PLTRST),
/* CAM1_RST */
PAD_CFG_GPO(GPP_R5, 1, PLTRST),
@@ -189,8 +185,6 @@
/* I2S0_RXD */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
- /* I2S2_SCLK */
- PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
/* I2S2_SFRM */
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* I2S2_TXD */