nb/intel/haswell: Allow using Broadwell MRC.bin
This is needed to support 9-series PCH-H (e.g. Z97) and Broadwell
non-ULT CPUs (for which more magic is required).
Tested on Asrock Z97 Extreme6: Boots, but ME has to be disabled so that
the system remains on after 30 seconds. Apparently, something Broadwell
MRC.bin does results in the ME being unhappy, as there is no such issue
when not using MRC.bin at all (native RAM init). S3 resume is working.
Change-Id: I7b33660099fa75c5ad46aeeda17b1215729f96c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 06c9999..d1c9ec2 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -37,6 +37,18 @@
binary is used meaning a jump is made from RW to the RO region
and back to the RW region after the binary is done.
+config USE_BROADWELL_MRC
+ bool "Use Broadwell MRC.bin"
+ depends on !USE_NATIVE_RAMINIT
+ help
+ Haswell MRC.bin has several limitations: it does not support
+ Broadwell CPUs nor 9-series PCHs, it does not initialise PEG
+ ports properly and it can't use more than one SPD file entry
+ at the same time (which would be useful for memory overclock
+ when using different DIMMs, without patching SPD EEPROMs). A
+ workaround for some of these limitations is to use Broadwell
+ MRC.bin instead.
+
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK