soc/intel/common/block: Add option to have subsystem_id in common pci driver
This patch ensures all Intel common PCI devices can
have subsystem ID programmed along with PCI resource
enabling (.enable_resources) as part of PCI enumeration
process.
TEST=Build and boot KBL/CNL/APL/GLK to ensure PCI
subsystem ID getting programmed.
Example:
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/590c
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 8086/591e
Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22768
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 9d54e11..6b886e3 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -89,13 +89,14 @@
}
static struct device_operations device_ops = {
- .read_resources = soc_lpc_read_resources,
- .set_resources = set_resources,
- .enable_resources = pci_dev_enable_resources,
- .write_acpi_tables = southbridge_write_acpi_tables,
- .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
- .init = lpc_init,
- .scan_bus = scan_lpc_bus,
+ .read_resources = soc_lpc_read_resources,
+ .set_resources = set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .write_acpi_tables = southbridge_write_acpi_tables,
+ .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+ .init = lpc_init,
+ .scan_bus = scan_lpc_bus,
+ .ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {