commit 6b688f5329e560ef432f6ea281b2fe3d905ef297
author Patrick Georgi <pgeorgi@google.com> Fri Feb 12 13:49:11 2021 +0100
committer Patrick Georgi <pgeorgi@google.com> Mon Feb 15 11:30:40 2021 +0000
tree 831ff654f7477b293421e38b8ed880f2cc740386
parent 036d66be051c4aeeac3b6220974e93645489c27d

src: use ARRAY_SIZE where possible

Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci

Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/amd/cimx/sb900/Sata.c

diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c
index 9d1655c..397ed7d 100644
--- a/src/vendorcode/amd/cimx/sb900/Sata.c
+++ b/src/vendorcode/amd/cimx/sb900/Sata.c
@@ -487,7 +487,7 @@
 
   // RPR 9.5 SATA PHY Programming Sequence
   pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]);
-  for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) {
+  for (i = 0; i < ARRAY_SIZE(sataPhyTable); i++) {
     RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80, AccWidthUint16 | S3_SAVE, 0x00, pPhyTable->wPhyCoreControl);
     RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune);
     ++pPhyTable;