tree 6e342ff1f2cfab461b79bfb268a4404a3099dcf1
parent 839c7f86044ab9e460d9ad905f77aa7f3f61aadb
author Subrata Banik <subratabanik@google.com> 1694809164 +0000
committer Subrata Banik <subratabanik@google.com> 1695365742 +0000

mb/google/rex: Add new FMD for prod (QS) Meteor Lake silicon

Intel Meteor Lake QS silicon provides better size optimized pre-x86
reset blobs.

This patch creates a new flash layout (FMD) for QS to accommodate those
optimizations, and renames the existing FMD for ES (pre-prod) silicon.

Comparative analysis between QS and ES flash layout is here:

For QS silicon:

 - SI_ALL reduced from 9MB to 8MB.
 - SI_BIOS increased by 1MB (from 23MB to 24MB) to fill in the 32MB SPI
   layout.
     - ME_RW_A/B reduce from ~4.5MB to 4MB.
     - Ensure RW-B slot is starting at 16MB boundary.
     - Unused space increased by 1MB.

For ES silicon:

 - SI_ALL: 9MB
 - SI_BIOS: 23MB
     - ME_RWA/B: 4.5MB (for ISH) and 4.4MB (non-ISH).
     - Unused space 3MB (for release) and 2MB (for debug) layout.

Change-Id: I881832a6b11a35710d4e847feadcc544b1f5d048
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77994
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>