mb/google/rex: Add new FMD for prod (QS) Meteor Lake silicon
Intel Meteor Lake QS silicon provides better size optimized pre-x86
reset blobs.
This patch creates a new flash layout (FMD) for QS to accommodate those
optimizations, and renames the existing FMD for ES (pre-prod) silicon.
Comparative analysis between QS and ES flash layout is here:
For QS silicon:
- SI_ALL reduced from 9MB to 8MB.
- SI_BIOS increased by 1MB (from 23MB to 24MB) to fill in the 32MB SPI
layout.
- ME_RW_A/B reduce from ~4.5MB to 4MB.
- Ensure RW-B slot is starting at 16MB boundary.
- Unused space increased by 1MB.
For ES silicon:
- SI_ALL: 9MB
- SI_BIOS: 23MB
- ME_RWA/B: 4.5MB (for ISH) and 4.4MB (non-ISH).
- Unused space 3MB (for release) and 2MB (for debug) layout.
Change-Id: I881832a6b11a35710d4e847feadcc544b1f5d048
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77994
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 3e4990d..edec6ac 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -121,6 +121,8 @@
default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
config FMDFILE
+ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos4es-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP && SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
+ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos4es.fmd" if CHROMEOS && SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
diff --git a/src/mainboard/google/rex/chromeos-debug-fsp.fmd b/src/mainboard/google/rex/chromeos-debug-fsp.fmd
index 3fbee83..37785fd 100644
--- a/src/mainboard/google/rex/chromeos-debug-fsp.fmd
+++ b/src/mainboard/google/rex/chromeos-debug-fsp.fmd
@@ -1,32 +1,14 @@
FLASH 32M {
- SI_ALL 9M {
+ SI_ALL 8M {
SI_DESC 16K
SI_ME
}
- SI_BIOS 23M {
+ SI_BIOS 24M {
RW_SECTION_A 7680K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
-#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
- ME_RW_A(CBFS) 4500K
-#else
- ME_RW_A(CBFS) 4400K
-#endif
- }
- # This section starts at the 16M boundary in SPI flash.
- # MTL does not support a region crossing this boundary,
- # because the SPI flash is memory-mapped into two non-
- # contiguous windows.
- RW_SECTION_B 7680K {
- VBLOCK_B 8K
- FW_MAIN_B(CBFS)
- RW_FWID_B 64
-#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
- ME_RW_B(CBFS) 4500K
-#else
- ME_RW_B(CBFS) 4400K
-#endif
+ ME_RW_A(CBFS) 4000K
}
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
@@ -46,8 +28,18 @@
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
+ # This section starts at the 16M boundary in SPI flash.
+ # MTL does not support a region crossing this boundary,
+ # because the SPI flash is memory-mapped into two non-
+ # contiguous windows.
+ RW_SECTION_B 7680K {
+ VBLOCK_B 8K
+ FW_MAIN_B(CBFS)
+ RW_FWID_B 64
+ ME_RW_B(CBFS) 4000K
+ }
RW_LEGACY(CBFS) 1M
- RW_UNUSED 2M
+ RW_UNUSED 3M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 4M {
diff --git a/src/mainboard/google/rex/chromeos.fmd b/src/mainboard/google/rex/chromeos.fmd
index 113bc72..6319553 100644
--- a/src/mainboard/google/rex/chromeos.fmd
+++ b/src/mainboard/google/rex/chromeos.fmd
@@ -1,32 +1,14 @@
FLASH 32M {
- SI_ALL 9M {
+ SI_ALL 8M {
SI_DESC 16K
SI_ME
}
- SI_BIOS 23M {
+ SI_BIOS 24M {
RW_SECTION_A 7M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
-#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
- ME_RW_A(CBFS) 4500K
-#else
- ME_RW_A(CBFS) 4400K
-#endif
- }
- # This section starts at the 16M boundary in SPI flash.
- # MTL does not support a region crossing this boundary,
- # because the SPI flash is memory-mapped into two non-
- # contiguous windows.
- RW_SECTION_B 7M {
- VBLOCK_B 8K
- FW_MAIN_B(CBFS)
- RW_FWID_B 64
-#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
- ME_RW_B(CBFS) 4500K
-#else
- ME_RW_B(CBFS) 4400K
-#endif
+ ME_RW_A(CBFS) 4000K
}
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
@@ -46,8 +28,18 @@
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
+ # This section starts at the 16M boundary in SPI flash.
+ # MTL does not support a region crossing this boundary,
+ # because the SPI flash is memory-mapped into two non-
+ # contiguous windows.
+ RW_SECTION_B 7M {
+ VBLOCK_B 8K
+ FW_MAIN_B(CBFS)
+ RW_FWID_B 64
+ ME_RW_B(CBFS) 4000K
+ }
RW_LEGACY(CBFS) 1M
- RW_UNUSED 3M
+ RW_UNUSED 4M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 4M {
diff --git a/src/mainboard/google/rex/chromeos4es-debug-fsp.fmd b/src/mainboard/google/rex/chromeos4es-debug-fsp.fmd
new file mode 100644
index 0000000..3fbee83
--- /dev/null
+++ b/src/mainboard/google/rex/chromeos4es-debug-fsp.fmd
@@ -0,0 +1,64 @@
+FLASH 32M {
+ SI_ALL 9M {
+ SI_DESC 16K
+ SI_ME
+ }
+ SI_BIOS 23M {
+ RW_SECTION_A 7680K {
+ VBLOCK_A 8K
+ FW_MAIN_A(CBFS)
+ RW_FWID_A 64
+#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
+ ME_RW_A(CBFS) 4500K
+#else
+ ME_RW_A(CBFS) 4400K
+#endif
+ }
+ # This section starts at the 16M boundary in SPI flash.
+ # MTL does not support a region crossing this boundary,
+ # because the SPI flash is memory-mapped into two non-
+ # contiguous windows.
+ RW_SECTION_B 7680K {
+ VBLOCK_B 8K
+ FW_MAIN_B(CBFS)
+ RW_FWID_B 64
+#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
+ ME_RW_B(CBFS) 4500K
+#else
+ ME_RW_B(CBFS) 4400K
+#endif
+ }
+ RW_MISC 1M {
+ UNIFIED_MRC_CACHE(PRESERVE) 128K {
+ RECOVERY_MRC_CACHE 64K
+ RW_MRC_CACHE 64K
+ }
+ RW_ELOG(PRESERVE) 16K
+ RW_SHARED 16K {
+ SHARED_DATA 8K
+ VBLOCK_DEV 8K
+ }
+ # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
+ # It is placed in the common `chromeos.fmd` file because it is only 4K and there
+ # is free space in the RW_MISC region that cannot be easily reclaimed because
+ # the RW_SECTION_B must start on the 16M boundary.
+ RW_SPD_CACHE(PRESERVE) 4K
+ RW_VPD(PRESERVE) 8K
+ RW_NVRAM(PRESERVE) 24K
+ }
+ RW_LEGACY(CBFS) 1M
+ RW_UNUSED 2M
+ # Make WP_RO region align with SPI vendor
+ # memory protected range specification.
+ WP_RO 4M {
+ RO_VPD(PRESERVE) 16K
+ RO_GSCVD 8K
+ RO_SECTION {
+ FMAP 2K
+ RO_FRID 64
+ GBB@4K 12K
+ COREBOOT(CBFS)
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/rex/chromeos4es.fmd b/src/mainboard/google/rex/chromeos4es.fmd
new file mode 100644
index 0000000..113bc72
--- /dev/null
+++ b/src/mainboard/google/rex/chromeos4es.fmd
@@ -0,0 +1,64 @@
+FLASH 32M {
+ SI_ALL 9M {
+ SI_DESC 16K
+ SI_ME
+ }
+ SI_BIOS 23M {
+ RW_SECTION_A 7M {
+ VBLOCK_A 8K
+ FW_MAIN_A(CBFS)
+ RW_FWID_A 64
+#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
+ ME_RW_A(CBFS) 4500K
+#else
+ ME_RW_A(CBFS) 4400K
+#endif
+ }
+ # This section starts at the 16M boundary in SPI flash.
+ # MTL does not support a region crossing this boundary,
+ # because the SPI flash is memory-mapped into two non-
+ # contiguous windows.
+ RW_SECTION_B 7M {
+ VBLOCK_B 8K
+ FW_MAIN_B(CBFS)
+ RW_FWID_B 64
+#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
+ ME_RW_B(CBFS) 4500K
+#else
+ ME_RW_B(CBFS) 4400K
+#endif
+ }
+ RW_MISC 1M {
+ UNIFIED_MRC_CACHE(PRESERVE) 128K {
+ RECOVERY_MRC_CACHE 64K
+ RW_MRC_CACHE 64K
+ }
+ RW_ELOG(PRESERVE) 16K
+ RW_SHARED 16K {
+ SHARED_DATA 8K
+ VBLOCK_DEV 8K
+ }
+ # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
+ # It is placed in the common `chromeos.fmd` file because it is only 4K and there
+ # is free space in the RW_MISC region that cannot be easily reclaimed because
+ # the RW_SECTION_B must start on the 16M boundary.
+ RW_SPD_CACHE(PRESERVE) 4K
+ RW_VPD(PRESERVE) 8K
+ RW_NVRAM(PRESERVE) 24K
+ }
+ RW_LEGACY(CBFS) 1M
+ RW_UNUSED 3M
+ # Make WP_RO region align with SPI vendor
+ # memory protected range specification.
+ WP_RO 4M {
+ RO_VPD(PRESERVE) 16K
+ RO_GSCVD 8K
+ RO_SECTION {
+ FMAP 2K
+ RO_FRID 64
+ GBB@4K 12K
+ COREBOOT(CBFS)
+ }
+ }
+ }
+}