commit 6b45ee44a9bbccb4dc42ea454aa20ef7d02a9fd1
author Subrata Banik <subrata.banik@intel.com> Fri May 12 11:43:57 2017 +0530
committer Martin Roth <martinroth@google.com> Tue May 16 17:45:38 2017 +0200
tree ef5eb4fa57c2bde345e5cec61668e33fe1d311b3
parent 481b364222322b96dc16ebc126040ed9c0aa2811

soc/intel/skylake: Add option to enable/disable EIST

Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.

Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/soc/intel/skylake/acpi.c

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index e8d0c16..64438bd 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -523,9 +523,10 @@
 			generate_c_state_entries(is_s0ix_enable,
 				max_c_state);
 
-			/* Generate P-state tables */
-			generate_p_state_entries(core_id,
-				cores_per_package);
+			if (config->eist_enable)
+				/* Generate P-state tables */
+				generate_p_state_entries(core_id,
+						cores_per_package);
 
 			acpigen_pop_len();
 		}

src/soc/intel/skylake/chip.h

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b474ca2..43c921e 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -459,6 +459,12 @@
 
 	/* Enable SGX feature */
 	u8 sgx_enable;
+
+	/* Enable/Disable EIST
+	 * 1b - Enabled
+	 * 0b - Disabled
+	 */
+	u8 eist_enable;
 };
 
 typedef struct soc_intel_skylake_config config_t;

src/soc/intel/skylake/chip_fsp20.c

diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 2d9b864..8a7cb21 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -261,6 +261,9 @@
 	/* Enable PMC XRAM read */
 	tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
 
+	/* Enable/Disable EIST */
+	tconfig->Eist = config->eist_enable;
+
 	soc_irq_settings(params);
 }
 

src/soc/intel/skylake/cpu.c

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index c472617..0572413 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -245,12 +245,17 @@
 
 static void configure_misc(void)
 {
+	device_t dev = SA_DEV_ROOT;
+	config_t *conf = dev->chip_info;
 	msr_t msr;
 
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
-	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+	if (conf->eist_enable)
+		msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+	else
+		msr.lo &= ~(1 << 16);	/* Enhanced SpeedStep Disable */
 	wrmsr(IA32_MISC_ENABLE, msr);
 
 	/* Disable Thermal interrupts */