tree f339fca6136e965e2dc965c0bd5874e62077c051
parent 601a971545e30057dda17e77de854a0bd1f5f226
author Felix Held <felix-coreboot@felixheld.de> 1639157896 +0100
committer Felix Held <felix-coreboot@felixheld.de> 1639607870 +0000

soc/amd/common/include/spi: add Cezanne-specific comment

The Cezanne PPR #56569 Rev 3.03 has one more SPI FIFO bytes defined
compared to the previous generations. It is unclear if adding some
special handling for Cezanne would be worth the effort, since the
current code just doesn't use the last byte which should be safe to do,
since this only affects the maximum number of bytes that can be used for
one SPI transaction. Having another byte to use on Cezanne wouldn't
reduce the number of SPI transactions to write a 256 byte data block.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic730f4fe838f59066120c811833995c132c84c1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>