soc/amd/common/block/lpc/lpc: drop custom lpc_set_resources
Drop the custom lpc_set_resources implementation that does some register
access that has no effect and then calls pci_dev_set_resources and use
pci_dev_set_resources for set_resources in amd_lpc_ops instead.
The SPI controller's base address got configured early in boot in the
lpc_set_spibase call and the enable bits got set early in boot in the
lpc_enable_spi_rom call.
TEST=The contents of the SPI_BASE_ADDRESS_REGISTER at the beginning and
at the end of the call stay the same, so it's simply a no-op.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7a5e3e00b2e38eeb3e9dae6d6c83d11ef925ce22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 3da3266..79a1d59 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -136,21 +136,6 @@
compact_resources(dev);
}
-static void lpc_set_resources(struct device *dev)
-{
- struct resource *res;
- u32 spi_enable_bits;
-
- /* Special case. The SpiRomEnable and other enables should STAY set. */
- res = find_resource(dev, 2);
- spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER);
- spi_enable_bits &= SPI_BASE_ALIGNMENT - 1;
- pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER,
- res->base | spi_enable_bits);
-
- pci_dev_set_resources(dev);
-}
-
static void configure_child_lpc_windows(struct device *dev, struct device *child)
{
struct resource *res;
@@ -329,7 +314,7 @@
struct device_operations amd_lpc_ops = {
.read_resources = lpc_read_resources,
- .set_resources = lpc_set_resources,
+ .set_resources = pci_dev_set_resources,
.enable_resources = lpc_enable_resources,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = lpc_acpi_name,