mb/google/poppy/variants/nami: Use GPP_B4 as Touchscreen Power Enable

Touchscreen power enable for Nami has moved from GBB_C22 to GPP_B4 in
the latest schematics.

BUG=b:74347464
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a

Change-Id: I3b1794d44f25c0d42d082d63b9e3ec3dfcef7528
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25154
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 8e2ebc1..602e41b 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -254,7 +254,7 @@
 				register "probed" = "1"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
 				register "reset_delay_ms" = "20"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)"
 				register "enable_delay_ms" = "1"
 				register "has_power_resource" = "1"
 				device i2c 10 on end
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index f0cf99f..8337e72 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -70,8 +70,8 @@
 	PAD_CFG_NC(GPP_B2),
 	/* B3  : CPU_GP2 ==> TOUCHSCREEN_RST# */
 	PAD_CFG_GPO(GPP_B3, 0, DEEP),
-	/* B4  : CPU_GP3 ==> NC */
-	PAD_CFG_NC(GPP_B4),
+	/* B4  : CPU_GP3 ==> EN_PP3300_DX_TOUCHSCREEN */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
 	/* B5  : SRCCLKREQ0# ==> NC */
 	PAD_CFG_NC(GPP_B5),
 	/* B6  : SRCCLKREQ1# ==> CLKREQ_PCIE#1 */
@@ -155,8 +155,8 @@
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 	/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-	/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
-	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+	/* C22 : UART2_RTS# ==> NC */
+	PAD_CFG_NC(GPP_C22),
 	/* C23 : UART2_CTS# ==> PCH_WP */
 	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),