This page gives some details about the [BeagleBone Black] coreboot port and describes how to build and run it.
The port currently only supports booting coreboot from a micro SD card and has some other limitations listed below.
The Beaglebone port supports the following boards:
This port was primarily developed as a learning exercise and there is potentially little reason to use it compared to the defacto bootloader choice of U-Boot. However, it does have some interesting practical use cases compared to U-Boot:
make menuconfig
and select TI/Beaglebone in the Mainboard menu.make
.build/MLO
file to the micro SD card at offset 128k - ie dd if=build/MLO of=/dev/sdcard seek=1 bs=128k
.NOTE: By default, the Beaglebone is configured to try to boot first from eMMC before booting from SD card. To ensure that the Beaglebone boots from SD, either erase the internal eMMC or hold the S2 button while powering on (note that this has to be while powering on - ie when plugging in the USB or DC barrel jack - the boot order doesn't change on reset) to prioritize SD in the boot order.
By default, coreboot uses UART0 as the serial console. UART0 is available through the J1 header on both the Beaglebone Black and Beaglebone Black Wireless. The serial runs at 3.3V and 115200 8n1.
The pin mapping is shown below for J1.
```eval_rst +----------------------------+------------+ | Pin number | Function | +============================+============+ | 1 (Closest to barrel jack) | GND | +----------------------------+------------+ | 4 | RX | +----------------------------+------------+ | 5 | TX | +----------------------------+------------+ ```
The AM335x contains ROM code to allow booting in a number of different configurations. More information about the boot ROM code can be found in the AM335x technical reference manual (SPRUH73Q) in the Initialization section.
This coreboot port is currently configured to boot in "SD Raw Mode" where the boot binary, with header ("Table of Contents" in TI's nomenclature), is placed at the offset of 0x20000 (128KB) on the SD card. The boot ROM loads the coreboot bootblock stage into SRAM and executes it.
The bootblock and subsequent romstage and ramstage coreboot stages expect that the coreboot image, containing the CBFS, is located at 0x20000 on the SD card. All stages directly read from the SD card in order to load the next stage in sequence.
To simplify the port, the TPS65217C Power Management IC (PMIC) on the Beaglebone Black is not configured by coreboot. By default, the PMIC reset values for VDD_MPU (1.1V) and VDD_CORE (1.8V) are within the Operating Performance Point (OPP) for the MPU PLL configuration set by the boot ROM of 500 MHz.
When using Linux as a payload, the kernel will appropriately scale the core voltages for the desired MPU clock frequency as defined in the device tree.
One significant difference because of this to the U-Boot port is that the DCDC1 rail that powers the DDR3 RAM will be 1.5V by default. The Micron DDR3 supports both 1.35V and 1.5V and U-Boot makes use of this by setting it to 1.35V to conserve power. Fortunately, Linux is again able to configure this rail but it involves adding an entry to the device tree:
&dcdc1_reg { regulator-name = "vdd_ddr3"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-boot-on; regulator-always-on; };
If this port was to be extended to work with boards or SoCs with different requirements for the MPU clock frequency or different Operating Performance Points, then the port may need to be extended to set the core voltages and MPU PLL within coreboot, prior to loading a payload. Extending coreboot so that it can configure the PMIC would also be necessary if there was a requirement for coreboot to run at a different MPU frequency than the 500 MHz set by the boot ROM.
mmc.c
driver to support running from both SD and eMMC.