tree d18028f987ebb97d6feadaabd6bd444de840d1b4
parent 211b64eeebc8ae18587d79a0dc9147dbffbd8249
author Reka Norman <rekanorman@google.com> 1654237869 +1000
committer Felix Held <felix-coreboot@felixheld.de> 1655298764 +0000

mb/google/nissa: Increase I2C bus frequency to around 390 kHz

- Set the speed to I2C_SPEED_FAST in each speed_config so that the
  speed_config is actually applied. Currently, the speed_config isn't
  applied, so the hcnt/lcnt calculation falls back to rise_time_ns and
  fall_time_ns, which are 0 since they're not set. This results in
  frequencies around 300 kHz.
- Move the data hold time to the speed_config, ensuring that the
  resulting sda_hold value remains the same.
- For nivviks and nereid, tune scl_lcnt and scl_hcnt for each bus to
  give a frequency around 390 kHz.
- In the baseboard, keep default scl_lcnt and scl_hcnt values. These
  work well for buses with a rise time around 100 ns, and can be used as
  a starting point before tuning them for a specific variant.

BUG=b:229547183
TEST=Measure the clock frequency, tHIGH, tLOW and tVD;DAT on nivviks
and nereid and check they meet the spec.

nereid clock frequencies:
I2C0 - 387.9 kHz
I2C1 - 392.7 kHz
I2C3 - 386.3 kHz
I2C5 - 383.6 kHz

nivviks clock frequencies:
I2C0 - 387.67 kHz
I2C1 - 380.47 kHz
I2C2 - 388.51 kHz
I2C3 - 384.03 kHz
I2C5 - 389.09 kHz

Change-Id: I88a6cfcc893183385eb85a89489e5d270277e537
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64942
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>