soc/amd/common: Create AcpiMmio functionality from stoneyridge
Move the stoneyridge AcpiMmio code into soc/amd/common.
The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000
commonly known as AcpiMmio. Implementations beginning with Mullins
enable decode in PMx04. Older designs use PMx24 and allow for
configuring the base address. Future work may support the older version.
Comparing the documentation for AMD's RRGs and BKDGs, it is evident that
the block locations have not been reassigned across products. In some
cases, address locations are deprecated and new ones consumed, e.g. the
early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks
are now at 0x1500, 0x1600, and 0x1700.
Note: Do not infer the definitions within the hardware blocks are
consistent across family/model products.
BUG=b:131682806
Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 29ab149..d4e1feb 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -46,6 +46,7 @@
select SOC_AMD_PI
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK
+ select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PI
select SOC_AMD_COMMON_BLOCK_PSP
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 227fb70..4f11ea2 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -28,6 +28,7 @@
#include <cbmem.h>
#include <device/device.h>
#include <device/pci.h>
+#include <amdblocks/acpimmio.h>
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index 285fedd..01ced08 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -16,13 +16,15 @@
*/
#include <device/mmio.h>
+#include <device/device.h>
#include <console/console.h>
#include <delay.h>
#include <gpio.h>
+#include <amdblocks/acpimmio.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
-#include <soc/southbridge.h>
#include <assert.h>
+#include "chip.h"
static const struct soc_amd_event gpio_event_table[] = {
{ GPIO_1, GEVENT_19 },
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index e6327dc..7762043 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -22,6 +22,9 @@
#define SPI_BASE_ADDRESS 0xfec10000
#define IO_APIC2_ADDR 0xfec20000
+/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */
+#include <amdblocks/acpimmio_map.h>
+
/* I2C fixed address */
#define I2C_BASE_ADDRESS 0xfedc2000
#define I2C_DEVICE_SIZE 0x00001000
@@ -32,30 +35,6 @@
#endif
#define HPET_BASE_ADDRESS 0xfed00000
-/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */
-#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
-#define ACPIMMIO_SM_PCI_BASE 0xfed80000
-#define ACPIMMIO_SMI_BASE 0xfed80200
-#define ACPIMMIO_PMIO_BASE 0xfed80300
-#define ACPIMMIO_PMIO2_BASE 0xfed80400
-#define ACPIMMIO_BIOSRAM_BASE 0xfed80500
-#define ACPIMMIO_CMOSRAM_BASE 0xfed80600
-#define ACPIMMIO_CMOS_BASE 0xfed80700
-#define ACPIMMIO_ACPI_BASE 0xfed80800
-#define ACPIMMIO_ASF_BASE 0xfed80900
-#define ACPIMMIO_SMBUS_BASE 0xfed80a00
-#define ACPIMMIO_WDT_BASE 0xfed80b00
-#define ACPIMMIO_HPET_BASE 0xfed80c00
-#define ACPIMMIO_IOMUX_BASE 0xfed80d00
-#define ACPIMMIO_MISC_BASE 0xfed80e00
-#define ACPIMMIO_DPVGA_BASE 0xfed81400
-#define ACPIMMIO_GPIO0_BASE 0xfed81500
-#define ACPIMMIO_GPIO1_BASE 0xfed81600
-#define ACPIMMIO_GPIO2_BASE 0xfed81700
-#define ACPIMMIO_XHCIPM_BASE 0xfed81c00
-#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00
-#define ACPIMMIO_AOAC_BASE 0xfed81e00
-
#define APU_UART0_BASE 0xfedc6000
#define APU_UART1_BASE 0xfedc8000
@@ -78,8 +57,6 @@
#define PM2_DATA 0xcd1
#define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5
-#define PM_INDEX 0xcd6
-#define PM_DATA 0xcd7
#define AB_INDX 0xcd8
#define AB_DATA (AB_INDX+4)
#define SYS_RESET 0xcf9
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 618a5de..6734efb 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -483,7 +483,6 @@
void southbridge_init(void *chip_info);
void sb_lpc_port80(void);
void sb_lpc_decode(void);
-void sb_acpi_mmio_decode(void);
void sb_pci_port80(void);
void sb_read_mode(u32 mode);
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
@@ -491,66 +490,8 @@
void sb_tpm_decode_spi(void);
void lpc_wideio_512_window(uint16_t base);
void lpc_wideio_16_window(uint16_t base);
-uint8_t pm_io_read8(uint8_t reg);
-uint16_t pm_io_read16(uint8_t reg);
-uint32_t pm_io_read32(uint8_t reg);
-void pm_io_write8(uint8_t reg, uint8_t value);
-void pm_io_write16(uint8_t reg, uint16_t value);
-void pm_io_write32(uint8_t reg, uint32_t value);
-u8 pm_read8(u8 reg);
-u16 pm_read16(u8 reg);
-u32 pm_read32(u8 reg);
-void pm_write8(u8 reg, u8 value);
-void pm_write16(u8 reg, u16 value);
-void pm_write32(u8 reg, u32 value);
-u8 acpi_read8(u8 reg);
-u16 acpi_read16(u8 reg);
-u32 acpi_read32(u8 reg);
-void acpi_write8(u8 reg, u8 value);
-void acpi_write16(u8 reg, u16 value);
-void acpi_write32(u8 reg, u32 value);
-u8 misc_read8(u8 reg);
-u16 misc_read16(u8 reg);
-u32 misc_read32(u8 reg);
-void misc_write8(u8 reg, u8 value);
-void misc_write16(u8 reg, u16 value);
-void misc_write32(u8 reg, u32 value);
-uint8_t smi_read8(uint8_t offset);
-uint16_t smi_read16(uint8_t offset);
-uint32_t smi_read32(uint8_t offset);
-void smi_write8(uint8_t offset, uint8_t value);
-void smi_write16(uint8_t offset, uint16_t value);
-void smi_write32(uint8_t offset, uint32_t value);
-uint8_t biosram_read8(uint8_t offset);
-void biosram_write8(uint8_t offset, uint8_t value);
-uint16_t biosram_read16(uint8_t offset);
-void biosram_write16(uint8_t offset, uint16_t value);
-uint32_t biosram_read32(uint8_t offset);
-void biosram_write32(uint8_t offset, uint32_t value);
uint16_t pm_acpi_pm_cnt_blk(void);
uint16_t pm_acpi_pm_evt_blk(void);
-void xhci_pm_write8(uint8_t reg, uint8_t value);
-uint8_t xhci_pm_read8(uint8_t reg);
-void xhci_pm_write16(uint8_t reg, uint16_t value);
-uint16_t xhci_pm_read16(uint8_t reg);
-void xhci_pm_write32(uint8_t reg, uint32_t value);
-uint32_t xhci_pm_read32(uint8_t reg);
-u8 iomux_read8(u8 reg);
-u16 iomux_read16(u8 reg);
-u32 iomux_read32(u8 reg);
-void iomux_write8(u8 reg, u8 value);
-void iomux_write16(u8 reg, u16 value);
-void iomux_write32(u8 reg, u32 value);
-uint8_t asf_read8(uint8_t offset);
-uint16_t asf_read16(uint8_t offset);
-void asf_write8(uint8_t offset, uint8_t value);
-void asf_write16(uint8_t offset, uint16_t value);
-uint8_t smbus_read8(uint8_t offset);
-uint16_t smbus_read16(uint8_t offset);
-void smbus_write8(uint8_t offset, uint8_t value);
-void smbus_write16(uint8_t offset, uint16_t value);
-uint8_t aoac_read8(uint8_t reg);
-void aoac_write8(uint8_t reg, uint8_t value);
void bootblock_fch_early_init(void);
void bootblock_fch_init(void);
/**
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index a838146..3ace1fd 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -27,6 +27,7 @@
#include <arch/ioapic.h>
#include <pc80/i8254.h>
#include <pc80/i8259.h>
+#include <amdblocks/acpimmio.h>
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c
index bfb5f42..7367251 100644
--- a/src/soc/amd/stoneyridge/pmutil.c
+++ b/src/soc/amd/stoneyridge/pmutil.c
@@ -15,6 +15,7 @@
#include <arch/acpi.h>
#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
#include <security/vboot/vboot_common.h>
#include <security/vboot/vbnv.h>
#include <pc80/mc146818rtc.h>
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index f43fcf3..7c855bb 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -25,7 +25,8 @@
#include <stage_cache.h>
#include <arch/bert_storage.h>
#include <soc/northbridge.h>
-#include <soc/southbridge.h>
+#include <soc/iomap.h>
+#include <amdblocks/acpimmio.h>
void backup_top_of_low_cacheable(uintptr_t ramtop)
{
diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c
index 34aa576..ec5ee91 100644
--- a/src/soc/amd/stoneyridge/reset.c
+++ b/src/soc/amd/stoneyridge/reset.c
@@ -20,6 +20,7 @@
#include <soc/pci_devs.h>
#include <device/pci_ops.h>
#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
#include <amdblocks/reset.h>
void set_warm_reset_flag(void)
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index 524efc4..11bf73a 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -16,358 +16,9 @@
#include <arch/io.h>
#include <device/mmio.h>
#include <arch/acpi.h>
+#include <amdblocks/acpimmio.h>
#include <soc/southbridge.h>
-/* PM registers are accessed a byte at a time via CD6/CD7 */
-uint8_t pm_io_read8(uint8_t reg)
-{
- outb(reg, PM_INDEX);
- return inb(PM_DATA);
-}
-
-uint16_t pm_io_read16(uint8_t reg)
-{
- return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg);
-}
-
-uint32_t pm_io_read32(uint8_t reg)
-{
- return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg);
-}
-
-void pm_io_write8(uint8_t reg, uint8_t value)
-{
- outb(reg, PM_INDEX);
- outb(value, PM_DATA);
-}
-
-void pm_io_write16(uint8_t reg, uint16_t value)
-{
- pm_io_write8(reg, value & 0xff);
- value >>= 8;
- pm_io_write8(reg + sizeof(uint8_t), value & 0xff);
-}
-
-void pm_io_write32(uint8_t reg, uint32_t value)
-{
- pm_io_write16(reg, value & 0xffff);
- value >>= 16;
- pm_io_write16(reg + sizeof(uint16_t), value & 0xffff);
-}
-
-/* smbus pci read/write - access registers at 0xfed80000 - currently unused */
-
-/* smi read/write - access registers at 0xfed80200 */
-
-uint8_t smi_read8(uint8_t offset)
-{
- return read8((void *)(ACPIMMIO_SMI_BASE + offset));
-}
-
-uint16_t smi_read16(uint8_t offset)
-{
- return read16((void *)(ACPIMMIO_SMI_BASE + offset));
-}
-
-uint32_t smi_read32(uint8_t offset)
-{
- return read32((void *)(ACPIMMIO_SMI_BASE + offset));
-}
-
-void smi_write8(uint8_t offset, uint8_t value)
-{
- write8((void *)(ACPIMMIO_SMI_BASE + offset), value);
-}
-
-void smi_write16(uint8_t offset, uint16_t value)
-{
- write16((void *)(ACPIMMIO_SMI_BASE + offset), value);
-}
-
-void smi_write32(uint8_t offset, uint32_t value)
-{
- write32((void *)(ACPIMMIO_SMI_BASE + offset), value);
-}
-
-/* pm read/write - access registers at 0xfed80300 */
-
-u8 pm_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_PMIO_BASE + reg));
-}
-
-u16 pm_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_PMIO_BASE + reg));
-}
-
-u32 pm_read32(u8 reg)
-{
- return read32((void *)(ACPIMMIO_PMIO_BASE + reg));
-}
-
-void pm_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_PMIO_BASE + reg), value);
-}
-
-void pm_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_PMIO_BASE + reg), value);
-}
-
-void pm_write32(u8 reg, u32 value)
-{
- write32((void *)(ACPIMMIO_PMIO_BASE + reg), value);
-}
-
-/* pm2 read/write - access registers at 0xfed80400 - currently unused */
-
-/* biosram read/write - access registers at 0xfed80500 */
-
-uint8_t biosram_read8(uint8_t offset)
-{
- return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset));
-}
-
-uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */
-{
- int i;
- uint16_t value = 0;
- for (i = sizeof(value) - 1 ; i >= 0 ; i--)
- value = (value << 8) | biosram_read8(offset + i);
- return value;
-}
-
-uint32_t biosram_read32(uint8_t offset)
-{
- uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16;
- return value | biosram_read16(offset);
-}
-
-void biosram_write8(uint8_t offset, uint8_t value)
-{
- write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value);
-}
-
-void biosram_write16(uint8_t offset, uint16_t value)
-{
- int i;
- for (i = 0 ; i < sizeof(value) ; i++) {
- biosram_write8(offset + i, value & 0xff);
- value >>= 8;
- }
-}
-
-void biosram_write32(uint8_t offset, uint32_t value)
-{
- int i;
- for (i = 0 ; i < sizeof(value) ; i++) {
- biosram_write8(offset + i, value & 0xff);
- value >>= 8;
- }
-}
-
-/* cmosram read/write - access registers at 0xfed80600 - currently unused */
-
-/* cmos read/write - access registers at 0xfed80700 - currently unused */
-
-/* acpi read/write - access registers at 0xfed80800 */
-
-u8 acpi_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_ACPI_BASE + reg));
-}
-
-u16 acpi_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_ACPI_BASE + reg));
-}
-
-u32 acpi_read32(u8 reg)
-{
- return read32((void *)(ACPIMMIO_ACPI_BASE + reg));
-}
-
-void acpi_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_ACPI_BASE + reg), value);
-}
-
-void acpi_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_ACPI_BASE + reg), value);
-}
-
-void acpi_write32(u8 reg, u32 value)
-{
- write32((void *)(ACPIMMIO_ACPI_BASE + reg), value);
-}
-
-/* asf read/write - access registers at 0xfed80900 - not currently used */
-
-u8 asf_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_ASF_BASE + reg));
-}
-
-u16 asf_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_ASF_BASE + reg));
-}
-
-void asf_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_ASF_BASE + reg), value);
-}
-
-void asf_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_ASF_BASE + reg), value);
-}
-
-/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */
-
-u8 smbus_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_SMBUS_BASE + reg));
-}
-
-u16 smbus_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_SMBUS_BASE + reg));
-}
-
-void smbus_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
-}
-
-void smbus_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
-}
-
-/* wdt read/write - access registers at 0xfed80b00 - not currently used */
-
-/* hpet read/write - access registers at 0xfed80c00 - not currently used */
-
-/* iomux read/write - access registers at 0xfed80d00 */
-
-u8 iomux_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_IOMUX_BASE + reg));
-}
-
-u16 iomux_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_IOMUX_BASE + reg));
-}
-
-u32 iomux_read32(u8 reg)
-{
- return read32((void *)(ACPIMMIO_IOMUX_BASE + reg));
-}
-
-void iomux_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
-}
-
-void iomux_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
-}
-
-void iomux_write32(u8 reg, u32 value)
-{
- write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
-}
-
-/* misc read/write - access registers at 0xfed80e00 */
-
-u8 misc_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_MISC_BASE + reg));
-}
-
-u16 misc_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_MISC_BASE + reg));
-}
-
-u32 misc_read32(u8 reg)
-{
- return read32((void *)(ACPIMMIO_MISC_BASE + reg));
-}
-
-void misc_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_MISC_BASE + reg), value);
-}
-
-void misc_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_MISC_BASE + reg), value);
-}
-
-void misc_write32(u8 reg, u32 value)
-{
- write32((void *)(ACPIMMIO_MISC_BASE + reg), value);
-}
-
-/* dpvga read/write - access registers at 0xfed81400 - not currently used */
-
-/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */
-/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */
-/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */
-
-/* xhci_pm read/write - access registers at 0xfed81c00 */
-
-uint8_t xhci_pm_read8(uint8_t reg)
-{
- return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg));
-}
-
-uint16_t xhci_pm_read16(uint8_t reg)
-{
- return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg));
-}
-
-uint32_t xhci_pm_read32(uint8_t reg)
-{
- return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg));
-}
-
-void xhci_pm_write8(uint8_t reg, uint8_t value)
-{
- write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
-}
-
-void xhci_pm_write16(uint8_t reg, uint16_t value)
-{
- write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
-}
-
-void xhci_pm_write32(uint8_t reg, uint32_t value)
-{
- write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
-}
-
-/* acdc_tmr read/write - access registers at 0xfed81d00 */
-
-/* aoac read/write - access registers at 0xfed81e00 - not currently used */
-
-u8 aoac_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_AOAC_BASE + reg));
-}
-
-void aoac_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_AOAC_BASE + reg), value);
-}
-
uint16_t pm_acpi_pm_cnt_blk(void)
{
return pm_read16(PM1_CNT_BLK);
diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c
index 6285d79..df7a86e 100644
--- a/src/soc/amd/stoneyridge/smbus.c
+++ b/src/soc/amd/stoneyridge/smbus.c
@@ -16,6 +16,7 @@
#include <arch/io.h>
#include <stdint.h>
#include <console/console.h>
+#include <amdblocks/acpimmio.h>
#include <soc/smbus.h>
#include <soc/southbridge.h>
diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c
index 5ddc0dd..4a0d833 100644
--- a/src/soc/amd/stoneyridge/smi.c
+++ b/src/soc/amd/stoneyridge/smi.c
@@ -19,6 +19,7 @@
*/
#include <console/console.h>
+#include <amdblocks/acpimmio.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c
index 91b86e2..8759e2a 100644
--- a/src/soc/amd/stoneyridge/smi_util.c
+++ b/src/soc/amd/stoneyridge/smi_util.c
@@ -21,6 +21,7 @@
#include <console/console.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
+#include <amdblocks/acpimmio.h>
void configure_smi(uint8_t smi_num, uint8_t mode)
{
diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c
index c3f4b67..c3aed57 100644
--- a/src/soc/amd/stoneyridge/smihandler.c
+++ b/src/soc/amd/stoneyridge/smihandler.c
@@ -24,6 +24,7 @@
#include <device/pci_def.h>
#include <soc/smi.h>
#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
#include <elog.h>
/* bits in smm_io_trap */
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index b6c40b6..bf8787c 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -27,6 +27,7 @@
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/reset.h>
+#include <amdblocks/acpimmio.h>
#include <soc/southbridge.h>
#include <soc/smbus.h>
#include <soc/smi.h>
@@ -359,16 +360,6 @@
pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp);
}
-void sb_acpi_mmio_decode(void)
-{
- uint8_t byte;
-
- /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */
- byte = pm_io_read8(PM_ISA_CONTROL);
- byte |= MMIO_EN;
- pm_io_write8(PM_ISA_CONTROL, byte);
-}
-
static void sb_enable_cf9_io(void)
{
uint32_t reg = pm_read32(PM_DECODE_EN);
@@ -642,7 +633,7 @@
sb_lpc_early_setup();
sb_spibase();
sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
- sb_acpi_mmio_decode();
+ enable_acpimmio_decode();
fch_smbus_init();
sb_enable_cf9_io();
setup_spread_spectrum(&reboot);
diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c
index f2fa3ba..00f8237 100644
--- a/src/soc/amd/stoneyridge/usb.c
+++ b/src/soc/amd/stoneyridge/usb.c
@@ -22,7 +22,7 @@
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
-
+#include <amdblocks/acpimmio.h>
static void set_usb_over_current(struct device *dev)
{